From ec946d5def460b52b400016396299a3e2ec70a35 Mon Sep 17 00:00:00 2001 From: Liphen Date: Thu, 30 Nov 2023 15:45:40 +0800 Subject: [PATCH] =?UTF-8?q?revert(icache):=20=E5=9B=9E=E9=80=80=E5=8F=96?= =?UTF-8?q?=E6=8C=87read=20next=20addr?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/cache/ICache.scala | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala index 8f36330..e31daed 100644 --- a/chisel/playground/src/cache/ICache.scala +++ b/chisel/playground/src/cache/ICache.scala @@ -17,11 +17,12 @@ class ICache(implicit config: CpuConfig) extends Module { val s_idle :: s_uncached :: s_save :: Nil = Enum(3) val status = RegInit(s_idle) - val read_next_addr = true.B // 未接入cache时默认使用下一个地址 - val araddr = Cat(io.cpu.addr(read_next_addr)(31, 2), 0.U(2.W)) + val read_next_addr = (status === s_idle || status === s_save) + val pc = Cat(io.cpu.addr(read_next_addr)(31, 2), 0.U(2.W)) // default val arvalid = RegInit(false.B) + val araddr = RegInit(0.U(AXI_ADDR_WID.W)) io.axi.ar.id := 0.U io.axi.ar.addr := araddr io.axi.ar.len := 0.U @@ -60,6 +61,7 @@ class ICache(implicit config: CpuConfig) extends Module { saved(0).valid := true.B status := s_save }.otherwise { + araddr := pc arvalid := true.B io.axi.ar.len := 0.U io.axi.ar.size := 2.U