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增加instrAddrMisaligned

This commit is contained in:
Liphen 2023-11-22 13:42:59 +08:00
parent fe0aa71511
commit e909de6dfb
6 changed files with 33 additions and 27 deletions
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1
chisel/playground/src/cache/ICache.scala vendored
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@ -18,6 +18,7 @@ class ICache(implicit config: CpuConfig) extends Module {
val status = RegInit(s_idle) val status = RegInit(s_idle)
io.cpu.valid.map(_ := status === s_finishwait) io.cpu.valid.map(_ := status === s_finishwait)
io.cpu.addr_err := io.cpu.addr(0)(1, 0).orR
val addr_err = io.cpu.addr(0).orR val addr_err = io.cpu.addr(0).orR
// default // default

37
chisel/playground/src/defines/Bundles.scala
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@ -22,19 +22,19 @@ class RdInfo extends Bundle {
} }
class InstInfo extends Bundle { class InstInfo extends Bundle {
val inst_valid = Bool() val inst_valid = Bool()
val reg1_ren = Bool() val reg1_ren = Bool()
val reg1_raddr = UInt(REG_ADDR_WID.W) val reg1_raddr = UInt(REG_ADDR_WID.W)
val reg2_ren = Bool() val reg2_ren = Bool()
val reg2_raddr = UInt(REG_ADDR_WID.W) val reg2_raddr = UInt(REG_ADDR_WID.W)
val fusel = FuType() val fusel = FuType()
val op = FuOpType() val op = FuOpType()
val reg_wen = Bool() val reg_wen = Bool()
val reg_waddr = UInt(REG_ADDR_WID.W) val reg_waddr = UInt(REG_ADDR_WID.W)
val imm = UInt(XLEN.W) val imm = UInt(XLEN.W)
val dual_issue = Bool() val dual_issue = Bool()
val inst = UInt(INST_WID.W) val inst = UInt(INST_WID.W)
val mem_wreg = Bool() val mem_wreg = Bool()
} }
class MemRead extends Bundle { class MemRead extends Bundle {
@ -107,14 +107,15 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
// read inst request from cpu // read inst request from cpu
val en = Output(Bool()) val en = Output(Bool())
val ready = Output(Bool()) val ready = Output(Bool())
val addr = Output(Vec(config.instFetchNum,UInt(INST_ADDR_WID.W))) // virtual address and next virtual address val addr = Output(Vec(config.instFetchNum, UInt(INST_ADDR_WID.W))) // virtual address and next virtual address
val fence_i = Output(Bool()) val fence_i = Output(Bool())
// read inst result // read inst result
val rdata = Input(Vec(config.instFetchNum,UInt(INST_WID.W))) val rdata = Input(Vec(config.instFetchNum, UInt(INST_WID.W)))
val valid = Input(Vec(config.instFetchNum,Bool())) val valid = Input(Vec(config.instFetchNum, Bool()))
val acc_err = Input(Bool()) val acc_err = Input(Bool())
val stall = Input(Bool()) val addr_err = Input(Bool())
val stall = Input(Bool())
} }
// cpu to dcache // cpu to dcache

6
chisel/playground/src/pipeline/decoder/DecoderUnit.scala
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@ -131,7 +131,8 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst0.ex.excode.map(_ := false.B) io.executeStage.inst0.ex.excode.map(_ := false.B)
io.executeStage.inst0.ex.excode(illegalInstr) := !decoder(0).io.out.inst_info.inst_valid && io.executeStage.inst0.ex.excode(illegalInstr) := !decoder(0).io.out.inst_info.inst_valid &&
!hasInt && !io.instFifo.info.empty !hasInt && !io.instFifo.info.empty
io.executeStage.inst0.ex.excode(instrAccessFault) := io.instFifo.inst(0).acc_err io.executeStage.inst0.ex.excode(instrAccessFault) := io.instFifo.inst(0).acc_err
io.executeStage.inst0.ex.excode(instrAddrMisaligned) := io.instFifo.inst(0).addr_err
io.executeStage.inst0.jb_info.jump_regiser := jumpCtrl.out.jump_register io.executeStage.inst0.jb_info.jump_regiser := jumpCtrl.out.jump_register
io.executeStage.inst0.jb_info.branch_inst := io.bpu.branch_inst io.executeStage.inst0.jb_info.branch_inst := io.bpu.branch_inst
@ -155,7 +156,8 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst1.ex.excode.map(_ := false.B) io.executeStage.inst1.ex.excode.map(_ := false.B)
io.executeStage.inst1.ex.excode(illegalInstr) := !decoder(1).io.out.inst_info.inst_valid && io.executeStage.inst1.ex.excode(illegalInstr) := !decoder(1).io.out.inst_info.inst_valid &&
!hasInt && !io.instFifo.info.almost_empty !hasInt && !io.instFifo.info.almost_empty
io.executeStage.inst1.ex.excode(instrAccessFault) := io.instFifo.inst(1).acc_err io.executeStage.inst1.ex.excode(instrAccessFault) := io.instFifo.inst(1).acc_err
io.executeStage.inst1.ex.excode(instrAddrMisaligned) := io.instFifo.inst(1).addr_err
} else { } else {
io.executeStage.inst1 := DontCare io.executeStage.inst1 := DontCare
} }

2
chisel/playground/src/pipeline/execute/ExecuteStage.scala
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@ -7,6 +7,7 @@ import cpu.defines.Const._
import cpu.{BranchPredictorConfig, CpuConfig} import cpu.{BranchPredictorConfig, CpuConfig}
class IdExeInst0 extends Bundle { class IdExeInst0 extends Bundle {
val valid = Bool()
val config = new BranchPredictorConfig() val config = new BranchPredictorConfig()
val pc = UInt(PC_WID.W) val pc = UInt(PC_WID.W)
val inst_info = new InstInfo() val inst_info = new InstInfo()
@ -24,6 +25,7 @@ class IdExeInst0 extends Bundle {
} }
class IdExeInst1 extends Bundle { class IdExeInst1 extends Bundle {
val valid = Bool()
val allow_to_go = Bool() val allow_to_go = Bool()
val pc = UInt(PC_WID.W) val pc = UInt(PC_WID.W)
val inst_info = new InstInfo() val inst_info = new InstInfo()

3
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
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@ -44,7 +44,6 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
io.ctrl.branch := io.ctrl.allow_to_go && io.ctrl.branch := io.ctrl.allow_to_go &&
(io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail) (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
io.csr.in.mtc0_wdata := io.executeStage.inst0.src_info.src2_data
io.csr.in.inst_info(0) := Mux( io.csr.in.inst_info(0) := Mux(
!io.executeStage.inst0.ex.flush_req, !io.executeStage.inst0.ex.flush_req,
io.executeStage.inst0.inst_info, io.executeStage.inst0.inst_info,
@ -79,7 +78,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
fu.inst(1).inst_info := io.executeStage.inst1.inst_info fu.inst(1).inst_info := io.executeStage.inst1.inst_info
fu.inst(1).src_info := io.executeStage.inst1.src_info fu.inst(1).src_info := io.executeStage.inst1.src_info
fu.inst(1).ex.in := io.executeStage.inst1.ex fu.inst(1).ex.in := io.executeStage.inst1.ex
fu.csr_rdata := io.csr.out.csr_rdata fu.csr_rdata := io.csr.out.rdata
fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch
io.bpu.pc := io.executeStage.inst0.pc io.bpu.pc := io.executeStage.inst0.pc

11
chisel/playground/src/pipeline/fetch/InstFifo.scala
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@ -10,13 +10,14 @@ class BufferUnit extends Bundle {
val inst = UInt(INST_WID.W) val inst = UInt(INST_WID.W)
val pht_index = UInt(bpuConfig.phtDepth.W) val pht_index = UInt(bpuConfig.phtDepth.W)
val acc_err = Bool() val acc_err = Bool()
val addr_err = Bool()
val pc = UInt(PC_WID.W) val pc = UInt(PC_WID.W)
} }
class InstFifo(implicit val config: CpuConfig) extends Module { class InstFifo(implicit val config: CpuConfig) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val do_flush = Input(Bool()) val do_flush = Input(Bool())
val icache_stall = Input(Bool()) val icache_stall = Input(Bool())
val ren = Input(Vec(config.decoderNum, Bool())) val ren = Input(Vec(config.decoderNum, Bool()))
val read = Output(Vec(config.decoderNum, new BufferUnit())) val read = Output(Vec(config.decoderNum, new BufferUnit()))
@ -46,7 +47,7 @@ class InstFifo(implicit val config: CpuConfig) extends Module {
io.read(0) := MuxCase( io.read(0) := MuxCase(
buffer(deq_ptr), buffer(deq_ptr),
Seq( Seq(
io.empty -> 0.U.asTypeOf(new BufferUnit()), io.empty -> 0.U.asTypeOf(new BufferUnit()),
io.almost_empty -> buffer(deq_ptr) io.almost_empty -> buffer(deq_ptr)
) )
) )
@ -61,8 +62,8 @@ class InstFifo(implicit val config: CpuConfig) extends Module {
0.U, 0.U,
Seq( Seq(
(io.empty) -> 0.U, (io.empty) -> 0.U,
io.ren(1) -> 2.U, io.ren(1) -> 2.U,
io.ren(0) -> 1.U io.ren(0) -> 1.U
) )
) )