From e909de6dfb4c21275ead5f4b51277d4bbfaf32b4 Mon Sep 17 00:00:00 2001 From: Liphen Date: Wed, 22 Nov 2023 13:42:59 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0instrAddrMisaligned?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/cache/ICache.scala | 1 + chisel/playground/src/defines/Bundles.scala | 37 ++++++++++--------- .../src/pipeline/decoder/DecoderUnit.scala | 6 ++- .../src/pipeline/execute/ExecuteStage.scala | 2 + .../src/pipeline/execute/ExecuteUnit.scala | 3 +- .../src/pipeline/fetch/InstFifo.scala | 11 +++--- 6 files changed, 33 insertions(+), 27 deletions(-) diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala index 05cc8ea..ea567c2 100644 --- a/chisel/playground/src/cache/ICache.scala +++ b/chisel/playground/src/cache/ICache.scala @@ -18,6 +18,7 @@ class ICache(implicit config: CpuConfig) extends Module { val status = RegInit(s_idle) io.cpu.valid.map(_ := status === s_finishwait) + io.cpu.addr_err := io.cpu.addr(0)(1, 0).orR val addr_err = io.cpu.addr(0).orR // default diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala index e5c647c..d17b574 100644 --- a/chisel/playground/src/defines/Bundles.scala +++ b/chisel/playground/src/defines/Bundles.scala @@ -22,19 +22,19 @@ class RdInfo extends Bundle { } class InstInfo extends Bundle { - val inst_valid = Bool() - val reg1_ren = Bool() - val reg1_raddr = UInt(REG_ADDR_WID.W) - val reg2_ren = Bool() - val reg2_raddr = UInt(REG_ADDR_WID.W) - val fusel = FuType() - val op = FuOpType() - val reg_wen = Bool() - val reg_waddr = UInt(REG_ADDR_WID.W) - val imm = UInt(XLEN.W) - val dual_issue = Bool() - val inst = UInt(INST_WID.W) - val mem_wreg = Bool() + val inst_valid = Bool() + val reg1_ren = Bool() + val reg1_raddr = UInt(REG_ADDR_WID.W) + val reg2_ren = Bool() + val reg2_raddr = UInt(REG_ADDR_WID.W) + val fusel = FuType() + val op = FuOpType() + val reg_wen = Bool() + val reg_waddr = UInt(REG_ADDR_WID.W) + val imm = UInt(XLEN.W) + val dual_issue = Bool() + val inst = UInt(INST_WID.W) + val mem_wreg = Bool() } class MemRead extends Bundle { @@ -107,14 +107,15 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle { // read inst request from cpu val en = Output(Bool()) val ready = Output(Bool()) - val addr = Output(Vec(config.instFetchNum,UInt(INST_ADDR_WID.W))) // virtual address and next virtual address + val addr = Output(Vec(config.instFetchNum, UInt(INST_ADDR_WID.W))) // virtual address and next virtual address val fence_i = Output(Bool()) // read inst result - val rdata = Input(Vec(config.instFetchNum,UInt(INST_WID.W))) - val valid = Input(Vec(config.instFetchNum,Bool())) - val acc_err = Input(Bool()) - val stall = Input(Bool()) + val rdata = Input(Vec(config.instFetchNum, UInt(INST_WID.W))) + val valid = Input(Vec(config.instFetchNum, Bool())) + val acc_err = Input(Bool()) + val addr_err = Input(Bool()) + val stall = Input(Bool()) } // cpu to dcache diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala index 870fe22..30a4b45 100644 --- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala +++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala @@ -131,7 +131,8 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti io.executeStage.inst0.ex.excode.map(_ := false.B) io.executeStage.inst0.ex.excode(illegalInstr) := !decoder(0).io.out.inst_info.inst_valid && !hasInt && !io.instFifo.info.empty - io.executeStage.inst0.ex.excode(instrAccessFault) := io.instFifo.inst(0).acc_err + io.executeStage.inst0.ex.excode(instrAccessFault) := io.instFifo.inst(0).acc_err + io.executeStage.inst0.ex.excode(instrAddrMisaligned) := io.instFifo.inst(0).addr_err io.executeStage.inst0.jb_info.jump_regiser := jumpCtrl.out.jump_register io.executeStage.inst0.jb_info.branch_inst := io.bpu.branch_inst @@ -155,7 +156,8 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti io.executeStage.inst1.ex.excode.map(_ := false.B) io.executeStage.inst1.ex.excode(illegalInstr) := !decoder(1).io.out.inst_info.inst_valid && !hasInt && !io.instFifo.info.almost_empty - io.executeStage.inst1.ex.excode(instrAccessFault) := io.instFifo.inst(1).acc_err + io.executeStage.inst1.ex.excode(instrAccessFault) := io.instFifo.inst(1).acc_err + io.executeStage.inst1.ex.excode(instrAddrMisaligned) := io.instFifo.inst(1).addr_err } else { io.executeStage.inst1 := DontCare } diff --git a/chisel/playground/src/pipeline/execute/ExecuteStage.scala b/chisel/playground/src/pipeline/execute/ExecuteStage.scala index f166948..22ecca4 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteStage.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteStage.scala @@ -7,6 +7,7 @@ import cpu.defines.Const._ import cpu.{BranchPredictorConfig, CpuConfig} class IdExeInst0 extends Bundle { + val valid = Bool() val config = new BranchPredictorConfig() val pc = UInt(PC_WID.W) val inst_info = new InstInfo() @@ -24,6 +25,7 @@ class IdExeInst0 extends Bundle { } class IdExeInst1 extends Bundle { + val valid = Bool() val allow_to_go = Bool() val pc = UInt(PC_WID.W) val inst_info = new InstInfo() diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala index 3df5f09..6b62330 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala @@ -44,7 +44,6 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module { io.ctrl.branch := io.ctrl.allow_to_go && (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail) - io.csr.in.mtc0_wdata := io.executeStage.inst0.src_info.src2_data io.csr.in.inst_info(0) := Mux( !io.executeStage.inst0.ex.flush_req, io.executeStage.inst0.inst_info, @@ -79,7 +78,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module { fu.inst(1).inst_info := io.executeStage.inst1.inst_info fu.inst(1).src_info := io.executeStage.inst1.src_info fu.inst(1).ex.in := io.executeStage.inst1.ex - fu.csr_rdata := io.csr.out.csr_rdata + fu.csr_rdata := io.csr.out.rdata fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch io.bpu.pc := io.executeStage.inst0.pc diff --git a/chisel/playground/src/pipeline/fetch/InstFifo.scala b/chisel/playground/src/pipeline/fetch/InstFifo.scala index 3bc1b06..6140cc3 100644 --- a/chisel/playground/src/pipeline/fetch/InstFifo.scala +++ b/chisel/playground/src/pipeline/fetch/InstFifo.scala @@ -10,13 +10,14 @@ class BufferUnit extends Bundle { val inst = UInt(INST_WID.W) val pht_index = UInt(bpuConfig.phtDepth.W) val acc_err = Bool() + val addr_err = Bool() val pc = UInt(PC_WID.W) } class InstFifo(implicit val config: CpuConfig) extends Module { val io = IO(new Bundle { - val do_flush = Input(Bool()) - val icache_stall = Input(Bool()) + val do_flush = Input(Bool()) + val icache_stall = Input(Bool()) val ren = Input(Vec(config.decoderNum, Bool())) val read = Output(Vec(config.decoderNum, new BufferUnit())) @@ -46,7 +47,7 @@ class InstFifo(implicit val config: CpuConfig) extends Module { io.read(0) := MuxCase( buffer(deq_ptr), Seq( - io.empty -> 0.U.asTypeOf(new BufferUnit()), + io.empty -> 0.U.asTypeOf(new BufferUnit()), io.almost_empty -> buffer(deq_ptr) ) ) @@ -61,8 +62,8 @@ class InstFifo(implicit val config: CpuConfig) extends Module { 0.U, Seq( (io.empty) -> 0.U, - io.ren(1) -> 2.U, - io.ren(0) -> 1.U + io.ren(1) -> 2.U, + io.ren(0) -> 1.U ) )