增加instrAddrMisaligned

chisel/playground/src/cache/ICache.scala

@@ -18,6 +18,7 @@ class ICache(implicit config: CpuConfig) extends Module {
   val status                                  = RegInit(s_idle)
 
   io.cpu.valid.map(_ := status === s_finishwait)
+  io.cpu.addr_err := io.cpu.addr(0)(1, 0).orR
   val addr_err = io.cpu.addr(0).orR
 
   // default

chisel/playground/src/defines/Bundles.scala

@@ -107,13 +107,14 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
   // read inst request from cpu
   val en      = Output(Bool())
   val ready   = Output(Bool())
-  val addr    = Output(Vec(config.instFetchNum,UInt(INST_ADDR_WID.W))) // virtual address and next virtual address
+  val addr    = Output(Vec(config.instFetchNum, UInt(INST_ADDR_WID.W))) // virtual address and next virtual address
   val fence_i = Output(Bool())
 
   // read inst result
-  val rdata   = Input(Vec(config.instFetchNum,UInt(INST_WID.W)))
+  val rdata    = Input(Vec(config.instFetchNum, UInt(INST_WID.W)))
-  val valid   = Input(Vec(config.instFetchNum,Bool()))
+  val valid    = Input(Vec(config.instFetchNum, Bool()))
   val acc_err  = Input(Bool())
+  val addr_err = Input(Bool())
   val stall    = Input(Bool())
 }
 

chisel/playground/src/pipeline/decoder/DecoderUnit.scala

@@ -132,6 +132,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   io.executeStage.inst0.ex.excode(illegalInstr) := !decoder(0).io.out.inst_info.inst_valid &&
     !hasInt && !io.instFifo.info.empty
   io.executeStage.inst0.ex.excode(instrAccessFault)    := io.instFifo.inst(0).acc_err
+  io.executeStage.inst0.ex.excode(instrAddrMisaligned) := io.instFifo.inst(0).addr_err
 
   io.executeStage.inst0.jb_info.jump_regiser     := jumpCtrl.out.jump_register
   io.executeStage.inst0.jb_info.branch_inst      := io.bpu.branch_inst
@@ -156,6 +157,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
     io.executeStage.inst1.ex.excode(illegalInstr) := !decoder(1).io.out.inst_info.inst_valid &&
     !hasInt && !io.instFifo.info.almost_empty
     io.executeStage.inst1.ex.excode(instrAccessFault)    := io.instFifo.inst(1).acc_err
+    io.executeStage.inst1.ex.excode(instrAddrMisaligned) := io.instFifo.inst(1).addr_err
   } else {
     io.executeStage.inst1 := DontCare
   }

chisel/playground/src/pipeline/execute/ExecuteStage.scala

@@ -7,6 +7,7 @@ import cpu.defines.Const._
 import cpu.{BranchPredictorConfig, CpuConfig}
 
 class IdExeInst0 extends Bundle {
+  val valid     = Bool()
   val config    = new BranchPredictorConfig()
   val pc        = UInt(PC_WID.W)
   val inst_info = new InstInfo()
@@ -24,6 +25,7 @@ class IdExeInst0 extends Bundle {
 }
 
 class IdExeInst1 extends Bundle {
+  val valid       = Bool()
   val allow_to_go = Bool()
   val pc          = UInt(PC_WID.W)
   val inst_info   = new InstInfo()

chisel/playground/src/pipeline/execute/ExecuteUnit.scala

@@ -44,7 +44,6 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   io.ctrl.branch := io.ctrl.allow_to_go &&
     (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
 
-  io.csr.in.mtc0_wdata := io.executeStage.inst0.src_info.src2_data
   io.csr.in.inst_info(0) := Mux(
     !io.executeStage.inst0.ex.flush_req,
     io.executeStage.inst0.inst_info,
@@ -79,7 +78,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   fu.inst(1).inst_info  := io.executeStage.inst1.inst_info
   fu.inst(1).src_info   := io.executeStage.inst1.src_info
   fu.inst(1).ex.in      := io.executeStage.inst1.ex
-  fu.csr_rdata          := io.csr.out.csr_rdata
+  fu.csr_rdata          := io.csr.out.rdata
   fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch
 
   io.bpu.pc               := io.executeStage.inst0.pc

chisel/playground/src/pipeline/fetch/InstFifo.scala

@@ -10,6 +10,7 @@ class BufferUnit extends Bundle {
   val inst      = UInt(INST_WID.W)
   val pht_index = UInt(bpuConfig.phtDepth.W)
   val acc_err   = Bool()
+  val addr_err  = Bool()
   val pc        = UInt(PC_WID.W)
 }