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fix(exe): 在exe提前访存

This commit is contained in:
Liphen 2023-12-25 21:19:31 +08:00
parent 35ca9a1732
commit e6a6f250c9
5 changed files with 33 additions and 12 deletions
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1
chisel/playground/src/Core.scala
View File

@ -119,6 +119,7 @@ class Core(implicit val config: CpuConfig) extends Module {
io.data.wdata := memoryUnit.dataMemory.out.wdata
io.data.addr := memoryUnit.dataMemory.out.addr
io.data.wstrb := memoryUnit.dataMemory.out.wstrb
io.data.exe_addr := executeUnit.dataMemory.addr
writeBackStage.memoryUnit <> memoryUnit.writeBackStage
writeBackStage.ctrl.allow_to_go := ctrl.writeBackUnit.allow_to_go

6
chisel/playground/src/cache/DCache.scala vendored
View File

@ -83,6 +83,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
// ==========================================================
val index = io.cpu.addr(indexWidth + offsetWidth - 1, offsetWidth)
val exe_addr = io.cpu.exe_addr(indexWidth + offsetWidth - 1, log2Ceil(XLEN / 8))
val bank_addr = io.cpu.addr(indexWidth + offsetWidth - 1, log2Ceil(XLEN / 8)) // TODO：目前临时使用一下
val bank_index = io.cpu.addr(bankIndexWidth + bankOffsetWidth - 1, bankOffsetWidth)
val bank_offset =
@ -136,15 +137,16 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
val ar_handshake = RegInit(false.B)
val aw_handshake = RegInit(false.B)
val should_next_addr = (state === s_idle && !tlb_fill) || (state === s_wait)
//
val data_raddr = Mux(victim.valid, victim_addr, bank_addr)
val data_raddr = Mux(victim.valid, victim_addr, Mux(should_next_addr, exe_addr, bank_addr))
val replace_wstrb = Wire(Vec(nway, UInt(AXI_STRB_WID.W)))
val replace_waddr = Mux(victim.valid, victim.waddr, bank_addr)
val replace_wdata = Mux(state === s_replace, io.axi.r.bits.data, io.cpu.wdata)
val replace_way = lru(index)
val tag_raddr = Mux(victim.valid, victim.index, index)
val tag_raddr = Mux(victim.valid, victim.index, Mux(should_next_addr, exe_addr, index))
val tag_wstrb = RegInit(VecInit(Seq.fill(nway)(false.B)))
val tag_wdata = RegInit(0.U(tagWidth.W))

1
chisel/playground/src/defines/Bundles.scala
View File

@ -120,6 +120,7 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
// cpu to dcache
class Cache_DCache extends Bundle {
val exe_addr = Output(UInt(DATA_ADDR_WID.W))
val addr = Output(UInt(DATA_ADDR_WID.W))
val rlen = Output(UInt(AXI_LEN_WID.W))
val en = Output(Bool())

5
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
View File

@ -31,6 +31,9 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
)
}
val memoryStage = Output(new ExecuteUnitMemoryUnit())
val dataMemory = new Bundle {
val addr = Output(UInt(DATA_ADDR_WID.W))
}
})
val fu = Module(new Fu()).io
@ -105,6 +108,8 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
fu.branch.jump_regiser := io.executeStage.inst0.jb_info.jump_regiser
fu.branch.branch_target := io.executeStage.inst0.jb_info.branch_target
io.dataMemory.addr := fu.dataMemory.addr
io.bpu.pc := io.executeStage.inst0.pc
io.bpu.update_pht_index := io.executeStage.inst0.jb_info.update_pht_index
io.bpu.branch := fu.branch.branch

12
chisel/playground/src/pipeline/execute/Fu.scala
View File

@ -22,6 +22,9 @@ class Fu(implicit val config: CpuConfig) extends Module {
}
)
val stall_req = Output(Bool())
val dataMemory = new Bundle {
val addr = Output(UInt(DATA_ADDR_WID.W))
}
val branch = new Bundle {
val pred_branch = Input(Bool())
val jump_regiser = Input(Bool())
@ -75,4 +78,13 @@ class Fu(implicit val config: CpuConfig) extends Module {
io.inst(1).result.alu := alu(1).io.result
io.inst(1).result.mdu := mdu.result
val mem_addr = Seq.tabulate(config.commitNum)(i =>
Mux(
LSUOpType.isLoad(io.inst(i).info.op),
io.inst(i).src_info.src1_data + io.inst(i).info.imm,
io.inst(i).src_info.src1_data
)
)
io.dataMemory.addr := Mux(io.inst(0).info.fusel === FuType.lsu, mem_addr(0), mem_addr(1))
}