diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala index 202741f..1f7165c 100644 --- a/chisel/playground/src/Core.scala +++ b/chisel/playground/src/Core.scala @@ -119,6 +119,7 @@ class Core(implicit val config: CpuConfig) extends Module { io.data.wdata := memoryUnit.dataMemory.out.wdata io.data.addr := memoryUnit.dataMemory.out.addr io.data.wstrb := memoryUnit.dataMemory.out.wstrb + io.data.exe_addr := executeUnit.dataMemory.addr writeBackStage.memoryUnit <> memoryUnit.writeBackStage writeBackStage.ctrl.allow_to_go := ctrl.writeBackUnit.allow_to_go diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala index c75beb6..4c9b79b 100644 --- a/chisel/playground/src/cache/DCache.scala +++ b/chisel/playground/src/cache/DCache.scala @@ -83,6 +83,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul // ========================================================== val index = io.cpu.addr(indexWidth + offsetWidth - 1, offsetWidth) + val exe_addr = io.cpu.exe_addr(indexWidth + offsetWidth - 1, log2Ceil(XLEN / 8)) val bank_addr = io.cpu.addr(indexWidth + offsetWidth - 1, log2Ceil(XLEN / 8)) // TODO：目前临时使用一下 val bank_index = io.cpu.addr(bankIndexWidth + bankOffsetWidth - 1, bankOffsetWidth) val bank_offset = @@ -136,15 +137,16 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul val ar_handshake = RegInit(false.B) val aw_handshake = RegInit(false.B) + val should_next_addr = (state === s_idle && !tlb_fill) || (state === s_wait) // - val data_raddr = Mux(victim.valid, victim_addr, bank_addr) + val data_raddr = Mux(victim.valid, victim_addr, Mux(should_next_addr, exe_addr, bank_addr)) val replace_wstrb = Wire(Vec(nway, UInt(AXI_STRB_WID.W))) val replace_waddr = Mux(victim.valid, victim.waddr, bank_addr) val replace_wdata = Mux(state === s_replace, io.axi.r.bits.data, io.cpu.wdata) val replace_way = lru(index) - val tag_raddr = Mux(victim.valid, victim.index, index) + val tag_raddr = Mux(victim.valid, victim.index, Mux(should_next_addr, exe_addr, index)) val tag_wstrb = RegInit(VecInit(Seq.fill(nway)(false.B))) val tag_wdata = RegInit(0.U(tagWidth.W)) diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala index a9821ab..e69af1e 100644 --- a/chisel/playground/src/defines/Bundles.scala +++ b/chisel/playground/src/defines/Bundles.scala @@ -103,10 +103,10 @@ class WriteBackCtrl extends Bundle { // cpu to icache class Cache_ICache(implicit val config: CpuConfig) extends Bundle { // read inst request from cpu - val req = Output(Bool()) + val req = Output(Bool()) val complete_single_request = Output(Bool()) // !cpu_stall - val addr = Output(Vec(config.instFetchNum, UInt(INST_ADDR_WID.W))) // virtual address and next virtual address - val fence = Output(Bool()) + val addr = Output(Vec(config.instFetchNum, UInt(INST_ADDR_WID.W))) // virtual address and next virtual address + val fence = Output(Bool()) // read inst result val inst = Input(Vec(config.instFetchNum, UInt(XLEN.W))) @@ -120,14 +120,15 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle { // cpu to dcache class Cache_DCache extends Bundle { - val addr = Output(UInt(DATA_ADDR_WID.W)) - val rlen = Output(UInt(AXI_LEN_WID.W)) - val en = Output(Bool()) - val wen = Output(Bool()) - val wdata = Output(UInt(XLEN.W)) + val exe_addr = Output(UInt(DATA_ADDR_WID.W)) + val addr = Output(UInt(DATA_ADDR_WID.W)) + val rlen = Output(UInt(AXI_LEN_WID.W)) + val en = Output(Bool()) + val wen = Output(Bool()) + val wdata = Output(UInt(XLEN.W)) val complete_single_request = Output(Bool()) - val fence = Output(Bool()) - val wstrb = Output(UInt(AXI_STRB_WID.W)) + val fence = Output(Bool()) + val wstrb = Output(UInt(AXI_STRB_WID.W)) val rdata = Input(UInt(XLEN.W)) val acc_err = Input(Bool()) diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala index d0d4198..88b174e 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala @@ -31,6 +31,9 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module { ) } val memoryStage = Output(new ExecuteUnitMemoryUnit()) + val dataMemory = new Bundle { + val addr = Output(UInt(DATA_ADDR_WID.W)) + } }) val fu = Module(new Fu()).io @@ -105,6 +108,8 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module { fu.branch.jump_regiser := io.executeStage.inst0.jb_info.jump_regiser fu.branch.branch_target := io.executeStage.inst0.jb_info.branch_target + io.dataMemory.addr := fu.dataMemory.addr + io.bpu.pc := io.executeStage.inst0.pc io.bpu.update_pht_index := io.executeStage.inst0.jb_info.update_pht_index io.bpu.branch := fu.branch.branch diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala index 25f0c1a..2943407 100644 --- a/chisel/playground/src/pipeline/execute/Fu.scala +++ b/chisel/playground/src/pipeline/execute/Fu.scala @@ -22,6 +22,9 @@ class Fu(implicit val config: CpuConfig) extends Module { } ) val stall_req = Output(Bool()) + val dataMemory = new Bundle { + val addr = Output(UInt(DATA_ADDR_WID.W)) + } val branch = new Bundle { val pred_branch = Input(Bool()) val jump_regiser = Input(Bool()) @@ -75,4 +78,13 @@ class Fu(implicit val config: CpuConfig) extends Module { io.inst(1).result.alu := alu(1).io.result io.inst(1).result.mdu := mdu.result + + val mem_addr = Seq.tabulate(config.commitNum)(i => + Mux( + LSUOpType.isLoad(io.inst(i).info.op), + io.inst(i).src_info.src1_data + io.inst(i).info.imm, + io.inst(i).src_info.src1_data + ) + ) + io.dataMemory.addr := Mux(io.inst(0).info.fusel === FuType.lsu, mem_addr(0), mem_addr(1)) }