fix(tlb): 修复数据宽度问题
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parent
e646ee4a4c
commit
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@ -4,6 +4,7 @@ import chisel3._
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import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.CacheConfig
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class DTlbL1 extends Module {
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val io = IO(new Bundle {
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@ -11,10 +12,17 @@ class DTlbL1 extends Module {
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val addr = Input(UInt(DATA_ADDR_WID.W))
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})
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val cacheConfig = CacheConfig("dcache")
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io.cache.uncached := AddressSpace.isMMIO(io.addr)
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io.cache.translation_ok := true.B
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io.cache.hit := true.B
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io.cache.tlb1_ok := true.B
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io.cache.tag := io.addr(XLEN - 1, 12)
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io.cache.pa := Cat(io.cache.tag, io.addr(11, 0))
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io.cache.tag := io.addr(PADDR_WID - 1, cacheConfig.offsetWidth + cacheConfig.indexWidth)
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io.cache.pa := Cat(io.cache.tag, io.addr(cacheConfig.offsetWidth + cacheConfig.indexWidth - 1, 0))
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println("----------------------------------------")
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println("DTlbL1")
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println("tag from " + (PADDR_WID - 1) + " to " + (cacheConfig.offsetWidth + cacheConfig.indexWidth))
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println("----------------------------------------")
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}
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@ -4,6 +4,7 @@ import chisel3._
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import chisel3.util._
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import cpu.defines._
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import cpu.defines.Const._
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import cpu.CacheConfig
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class ITlbL1 extends Module {
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val io = IO(new Bundle {
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@ -11,9 +12,16 @@ class ITlbL1 extends Module {
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val cache = new Tlb_ICache()
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})
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val cacheConfig = CacheConfig("icache")
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io.cache.uncached := AddressSpace.isMMIO(io.addr)
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io.cache.translation_ok := true.B
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io.cache.hit := true.B
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io.cache.tag := io.addr(XLEN - 1, 12)
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io.cache.pa := Cat(io.cache.tag, io.addr(11, 0))
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io.cache.tag := io.addr(PADDR_WID - 1, cacheConfig.offsetWidth + cacheConfig.indexWidth)
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io.cache.pa := Cat(io.cache.tag, io.addr(cacheConfig.offsetWidth + cacheConfig.indexWidth - 1, 0))
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println("----------------------------------------")
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println("ITlbL1")
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println("tag from " + (PADDR_WID - 1) + " to " + (cacheConfig.offsetWidth + cacheConfig.indexWidth))
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println("----------------------------------------")
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}
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@ -2,6 +2,8 @@ package cpu.defines
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import chisel3._
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import chisel3.util._
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import cpu.defines.Const._
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import cpu.CacheConfig
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sealed trait Sv39Const extends CoreParameter {
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val PAddrBits = PADDR_WID
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@ -113,23 +115,26 @@ sealed trait Sv39Const extends CoreParameter {
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}
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class Tlb_ICache extends Bundle {
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val fill = Input(Bool())
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val icache_is_save = Input(Bool())
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val uncached = Output(Bool())
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val cacheConfig = CacheConfig("icache")
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val fill = Input(Bool())
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val uncached = Output(Bool())
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val translation_ok = Output(Bool())
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val hit = Output(Bool())
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val tag = Output(UInt(20.W))
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val pa = Output(UInt(32.W))
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val tag = Output(UInt(cacheConfig.tagWidth.W))
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val pa = Output(UInt(PADDR_WID.W))
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}
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class Tlb_DCache extends Bundle {
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val fill = Input(Bool())
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val uncached = Output(Bool())
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val tlb1_ok = Output(Bool())
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val cacheConfig = CacheConfig("dcache")
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val fill = Input(Bool())
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val uncached = Output(Bool())
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val tlb1_ok = Output(Bool())
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val translation_ok = Output(Bool())
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val hit = Output(Bool())
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val tag = Output(UInt(20.W))
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val pa = Output(UInt(32.W))
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val tag = Output(UInt(cacheConfig.tagWidth.W))
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val pa = Output(UInt(PADDR_WID.W))
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}
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