yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Remove unused variables in Core and Csr classes

This commit is contained in:
Liphen 2023-12-11 15:08:56 +08:00
parent 7df36c2c38
commit cface2454d
2 changed files with 0 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
chisel/playground/src/Core.scala
View File

@ -103,8 +103,6 @@ class Core(implicit val config: CpuConfig) extends Module {
memoryUnit.csr <> csr.memoryUnit memoryUnit.csr <> csr.memoryUnit
memoryUnit.writeBackStage <> writeBackStage.memoryUnit memoryUnit.writeBackStage <> writeBackStage.memoryUnit
csr.ctrl.exe_stall := !ctrl.executeUnit.allow_to_go
csr.ctrl.mem_stall := !ctrl.memoryUnit.allow_to_go
csr.ext_int := io.ext_int csr.ext_int := io.ext_int
memoryUnit.dataMemory.in.rdata := io.data.rdata memoryUnit.dataMemory.in.rdata := io.data.rdata

2
chisel/playground/src/pipeline/execute/Csr.scala
View File

@ -251,8 +251,6 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
val addr = io.executeUnit.in.info.inst(31, 20) val addr = io.executeUnit.in.info.inst(31, 20)
val src1 = io.executeUnit.in.src_info.src1_data val src1 = io.executeUnit.in.src_info.src1_data
val csri = ZeroExtend(io.executeUnit.in.info.inst(19, 15), XLEN) val csri = ZeroExtend(io.executeUnit.in.info.inst(19, 15), XLEN)
val exe_stall = io.ctrl.exe_stall
val mem_stall = io.ctrl.mem_stall
wdata := LookupTree( wdata := LookupTree(
op, op,
List( List(