From cface2454d20636603911165be78977652711748 Mon Sep 17 00:00:00 2001 From: Liphen Date: Mon, 11 Dec 2023 15:08:56 +0800 Subject: [PATCH] Remove unused variables in Core and Csr classes --- chisel/playground/src/Core.scala | 2 -- chisel/playground/src/pipeline/execute/Csr.scala | 2 -- 2 files changed, 4 deletions(-) diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala index 06178b6..f2d0b16 100644 --- a/chisel/playground/src/Core.scala +++ b/chisel/playground/src/Core.scala @@ -103,8 +103,6 @@ class Core(implicit val config: CpuConfig) extends Module { memoryUnit.csr <> csr.memoryUnit memoryUnit.writeBackStage <> writeBackStage.memoryUnit - csr.ctrl.exe_stall := !ctrl.executeUnit.allow_to_go - csr.ctrl.mem_stall := !ctrl.memoryUnit.allow_to_go csr.ext_int := io.ext_int memoryUnit.dataMemory.in.rdata := io.data.rdata diff --git a/chisel/playground/src/pipeline/execute/Csr.scala b/chisel/playground/src/pipeline/execute/Csr.scala index db2efb7..3e43165 100644 --- a/chisel/playground/src/pipeline/execute/Csr.scala +++ b/chisel/playground/src/pipeline/execute/Csr.scala @@ -251,8 +251,6 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst { val addr = io.executeUnit.in.info.inst(31, 20) val src1 = io.executeUnit.in.src_info.src1_data val csri = ZeroExtend(io.executeUnit.in.info.inst(19, 15), XLEN) - val exe_stall = io.ctrl.exe_stall - val mem_stall = io.ctrl.mem_stall wdata := LookupTree( op, List(