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perf(CacheConfig): 将所有的定义搬至config中

This commit is contained in:
Liphen 2023-12-24 15:20:27 +08:00
parent 03ccee30f6
commit c1cf6f8b7d
2 changed files with 17 additions and 14 deletions
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23
chisel/playground/src/CpuConfig.scala
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@ -28,18 +28,25 @@ case class BranchPredictorConfig(
val phtDepth: Int = 6) val phtDepth: Int = 6)
case class CacheConfig( case class CacheConfig(
nway: Int = 2, // 路数，目前只支持2路 cacheType: String = "icache" // icache, dcache
nbank: Int, // 每个项目中的bank数
nindex: Int, // 每路的项目数
bytesPerBank: Int // 每个bank中的字节数
) { ) {
val config = CpuConfig() // ==========================================================
// | tag | index | offset |
// | | | bank index | bank offset |
// ==========================================================
val config = CpuConfig()
val nway = 2 // 路数，目前只支持2路
val nbank = if (cacheType == "icache") 4 else 8 // 每个项目中的bank数
val nindex = if (cacheType == "icache") 64 else 128 // 每路的项目数
val bitsPerBank = // 每个bank的位数
if (cacheType == "icache") INST_WID * config.instFetchNum
else XLEN
val bytesPerBank = bitsPerBank / 8 //每个bank中的字节数
val indexWidth = log2Ceil(nindex) // index的位宽 val indexWidth = log2Ceil(nindex) // index的位宽
val bankIndexWidth = log2Ceil(nbank) val bankIndexWidth = log2Ceil(nbank) // bank index的位宽
val bankOffsetWidth = log2Ceil(bytesPerBank) val bankOffsetWidth = log2Ceil(bytesPerBank) // bank offset的位宽
val offsetWidth = bankIndexWidth + bankOffsetWidth // offset的位宽 val offsetWidth = bankIndexWidth + bankOffsetWidth // offset的位宽
val tagWidth = 32 - indexWidth - offsetWidth // tag的位宽 val tagWidth = 32 - indexWidth - offsetWidth // tag的位宽
val bitsPerBank = bytesPerBank * 8
require(isPow2(nindex)) require(isPow2(nindex))
require(isPow2(nway)) require(isPow2(nway))
require(isPow2(nbank)) require(isPow2(nbank))

8
chisel/playground/src/cache/Cache.scala vendored
View File

@ -14,12 +14,8 @@ class Cache(implicit config: CpuConfig) extends Module {
val axi = new AXI() val axi = new AXI()
}) })
// 每个 bank 存 2 条 32 bit 指令 implicit val iCacheConfig = CacheConfig(cacheType = "icache")
implicit val iCacheConfig = implicit val dCacheConfig = CacheConfig(cacheType = "dcache")
CacheConfig(nindex = 64, nbank = 4, bytesPerBank = (INST_WID / 8) * config.instFetchNum)
// 每个 bank 存 1 条 XLEN bit 数据
implicit val dCacheConfig =
CacheConfig(nindex = 128, nbank = 8, bytesPerBank = XLEN / 8)
val icache = Module(new ICache(iCacheConfig)) val icache = Module(new ICache(iCacheConfig))
val dcache = Module(new DCache(dCacheConfig)) val dcache = Module(new DCache(dCacheConfig))