diff --git a/chisel/playground/src/CpuConfig.scala b/chisel/playground/src/CpuConfig.scala
index 595d5a0..2833034 100644
--- a/chisel/playground/src/CpuConfig.scala
+++ b/chisel/playground/src/CpuConfig.scala
@@ -28,18 +28,25 @@ case class BranchPredictorConfig(
   val phtDepth: Int = 6)
 
 case class CacheConfig(
-  nway:         Int = 2, // 路数，目前只支持2路
-  nbank:        Int, // 每个项目中的bank数
-  nindex:       Int, // 每路的项目数
-  bytesPerBank: Int // 每个bank中的字节数
+  cacheType: String = "icache" // icache, dcache
 ) {
-  val config          = CpuConfig()
+// ==========================================================
+// |        tag         |  index |         offset           |
+// |                    |        | bank index | bank offset |
+// ==========================================================
+  val config = CpuConfig()
+  val nway   = 2 // 路数，目前只支持2路
+  val nbank  = if (cacheType == "icache") 4 else 8 // 每个项目中的bank数
+  val nindex = if (cacheType == "icache") 64 else 128 // 每路的项目数
+  val bitsPerBank = // 每个bank的位数
+    if (cacheType == "icache") INST_WID * config.instFetchNum
+    else XLEN
+  val bytesPerBank    = bitsPerBank / 8 //每个bank中的字节数
   val indexWidth      = log2Ceil(nindex) // index的位宽
-  val bankIndexWidth  = log2Ceil(nbank)
-  val bankOffsetWidth = log2Ceil(bytesPerBank)
+  val bankIndexWidth  = log2Ceil(nbank) // bank index的位宽
+  val bankOffsetWidth = log2Ceil(bytesPerBank) // bank offset的位宽
   val offsetWidth     = bankIndexWidth + bankOffsetWidth // offset的位宽
   val tagWidth        = 32 - indexWidth - offsetWidth // tag的位宽
-  val bitsPerBank     = bytesPerBank * 8
   require(isPow2(nindex))
   require(isPow2(nway))
   require(isPow2(nbank))
diff --git a/chisel/playground/src/cache/Cache.scala b/chisel/playground/src/cache/Cache.scala
index ec94b17..1131f96 100644
--- a/chisel/playground/src/cache/Cache.scala
+++ b/chisel/playground/src/cache/Cache.scala
@@ -14,12 +14,8 @@ class Cache(implicit config: CpuConfig) extends Module {
     val axi  = new AXI()
   })
 
-  // 每个 bank 存 2 条 32 bit 指令
-  implicit val iCacheConfig =
-    CacheConfig(nindex = 64, nbank = 4, bytesPerBank = (INST_WID / 8) * config.instFetchNum)
-  // 每个 bank 存 1 条 XLEN bit 数据
-  implicit val dCacheConfig =
-    CacheConfig(nindex = 128, nbank = 8, bytesPerBank = XLEN / 8)
+  implicit val iCacheConfig = CacheConfig(cacheType = "icache")
+  implicit val dCacheConfig = CacheConfig(cacheType = "dcache")
 
   val icache        = Module(new ICache(iCacheConfig))
   val dcache        = Module(new DCache(dCacheConfig))