refactor: 部分常量换成XLEN

chisel/playground/src/cache/DCache.scala

@@ -9,7 +9,7 @@ import cpu.CpuConfig
 import cpu.defines.Const._
 
 class WriteBufferUnit extends Bundle {
-  val data = UInt(DATA_WID.W)
+  val data = UInt(XLEN.W)
   val addr = UInt(DATA_ADDR_WID.W)
   val strb = UInt(4.W)
   val size = UInt(2.W)
@@ -68,7 +68,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
     val working = Bool()
   }))
 
-  val read_buffer  = RegInit(VecInit(Seq.fill(16)(0.U(DATA_WID.W))))
+  val read_buffer  = RegInit(VecInit(Seq.fill(16)(0.U(XLEN.W))))
   val ar_handshake = RegInit(false.B)
   val aw_handshake = RegInit(false.B)
 
@@ -81,7 +81,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
   val tag_wstrb = RegInit(VecInit(Seq.fill(nway)(false.B)))
   val tag_wdata = RegInit(0.U(tagWidth.W))
 
-  val data = Wire(Vec(nway, UInt(DATA_WID.W)))
+  val data = Wire(Vec(nway, UInt(XLEN.W)))
   val tag  = RegInit(VecInit(Seq.fill(nway)(0.U(tagWidth.W))))
 
   val tag_compare_valid = Wire(Vec(nway, Bool()))
@@ -103,13 +103,13 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
   )
   io.cpu.dcache_ready := !dcache_stall
 
-  val saved_rdata = RegInit(0.U(DATA_WID.W))
+  val saved_rdata = RegInit(0.U(XLEN.W))
 
   // forward last stored data in data bram
   val last_waddr         = RegNext(data_waddr)
-  val last_wstrb         = RegInit(VecInit(Seq.fill(nway)(0.U(DATA_WID.W))))
+  val last_wstrb         = RegInit(VecInit(Seq.fill(nway)(0.U(XLEN.W))))
   val last_wdata         = RegNext(data_wdata)
-  val cache_data_forward = Wire(Vec(nway, UInt(DATA_WID.W)))
+  val cache_data_forward = Wire(Vec(nway, UInt(XLEN.W)))
 
   io.cpu.rdata := cache_data_forward(sel)
 

chisel/playground/src/cache/ICache.scala

@@ -51,7 +51,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
   val instperbank = bankWidth / 4 // 每个bank存储的指令数
   val valid       = RegInit(VecInit(Seq.fill(nset * nbank)(VecInit(Seq.fill(instperbank)(false.B)))))
 
-  val data = Wire(Vec(nway, Vec(instperbank, UInt(DATA_WID.W))))
+  val data = Wire(Vec(nway, Vec(instperbank, UInt(XLEN.W))))
   val tag  = RegInit(VecInit(Seq.fill(nway)(0.U(tagWidth.W))))
 
   // * should choose next addr * //
@@ -96,7 +96,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
   val inst_valid = VecInit(Seq.tabulate(instperbank)(i => cache_hit_available && i.U <= (3.U - bank_offset)))
 
   val saved = RegInit(VecInit(Seq.fill(instperbank)(0.U.asTypeOf(new Bundle {
-    val inst  = UInt(PC_WID.W)
+    val inst  = UInt(INST_WID.W)
     val valid = Bool()
   }))))
 
@@ -104,7 +104,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
 
   // bank tag ram
   for { i <- 0 until nway; j <- 0 until instperbank } {
-    val bank = Module(new SimpleDualPortRam(nset * nbank, INST_BANK_WID, byteAddressable = true))
+    val bank = Module(new SimpleDualPortRam(nset * nbank, INST_WID, byteAddressable = true))
     bank.io.ren   := true.B
     bank.io.raddr := data_raddr
     data(i)(j)    := bank.io.rdata
@@ -208,7 +208,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul
       }.elsewhen(io.axi.r.fire) {
         // * uncached not support burst transport * //
         state          := s_save
-        saved(0).inst  := io.axi.r.bits.data
+        saved(0).inst  := Mux(ar.addr(2), io.axi.r.bits.data(63, 32), io.axi.r.bits.data(31, 0))
         saved(0).valid := true.B
         rready         := false.B
         acc_err        := io.axi.r.bits.resp =/= RESP_OKEY.U

chisel/playground/src/defines/Bundles.scala

@@ -39,7 +39,7 @@ class InstInfo extends Bundle {
   val reg_wen    = Bool()
   val reg_waddr  = UInt(REG_ADDR_WID.W)
   val imm        = UInt(XLEN.W)
-  val inst       = UInt(INST_WID.W)
+  val inst       = UInt(XLEN.W)
 }
 
 class MemRead extends Bundle {
@@ -109,7 +109,7 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
   val fence     = Output(Bool())
 
   // read inst result
-  val inst         = Input(Vec(config.instFetchNum, UInt(INST_WID.W)))
+  val inst         = Input(Vec(config.instFetchNum, UInt(XLEN.W)))
   val inst_valid   = Input(Vec(config.instFetchNum, Bool()))
   val acc_err      = Input(Bool())
   val icache_stall = Input(Bool()) // icache_stall
@@ -210,5 +210,5 @@ class DEBUG extends Bundle {
   val wb_pc       = Output(UInt(PC_WID.W))
   val wb_rf_wen   = Output(Bool())
   val wb_rf_wnum  = Output(UInt(REG_ADDR_WID.W))
-  val wb_rf_wdata = Output(UInt(DATA_WID.W))
+  val wb_rf_wdata = Output(UInt(XLEN.W))
 }

chisel/playground/src/defines/Const.scala

@@ -20,7 +20,6 @@ trait Constants extends CoreParameter {
   val EXC_WID = 16
 
   // inst rom
-  val INST_BANK_WID = 32
   val INST_WID      = XLEN
   val INST_ADDR_WID = XLEN
 
@@ -30,7 +29,6 @@ trait Constants extends CoreParameter {
   // GPR RegFile
   val AREG_NUM     = 32
   val REG_ADDR_WID = 5
-  val DATA_WID     = XLEN
 }
 
 trait AXIConst {

chisel/playground/src/pipeline/decoder/ARegfile.scala

@@ -8,7 +8,7 @@ import cpu.CpuConfig
 
 class SrcRead extends Bundle {
   val raddr = Output(UInt(REG_ADDR_WID.W))
-  val rdata = Input(UInt(DATA_WID.W))
+  val rdata = Input(UInt(XLEN.W))
 }
 
 class Src12Read extends Bundle {
@@ -19,7 +19,7 @@ class Src12Read extends Bundle {
 class RegWrite extends Bundle {
   val wen   = Output(Bool())
   val waddr = Output(UInt(REG_ADDR_WID.W))
-  val wdata = Output(UInt(DATA_WID.W))
+  val wdata = Output(UInt(XLEN.W))
 }
 
 class ARegFile(implicit val config: CpuConfig) extends Module {
@@ -29,7 +29,7 @@ class ARegFile(implicit val config: CpuConfig) extends Module {
   })
 
   // 定义32个32位寄存器
-  val regs = RegInit(VecInit(Seq.fill(AREG_NUM)(0.U(DATA_WID.W))))
+  val regs = RegInit(VecInit(Seq.fill(AREG_NUM)(0.U(XLEN.W))))
 
   // 写寄存器堆
   for (i <- 0 until (config.commitNum)) {

chisel/playground/src/pipeline/decoder/Decoder.scala

@@ -9,7 +9,7 @@ class Decoder extends Module with HasInstrType {
   val io = IO(new Bundle {
     // inputs
     val in = Input(new Bundle {
-      val inst = UInt(INST_WID.W)
+      val inst = UInt(XLEN.W)
     })
     // outputs
     val out = Output(new Bundle {

chisel/playground/src/pipeline/execute/ALU.scala

@@ -9,7 +9,7 @@ class Alu extends Module {
   val io = IO(new Bundle {
     val info     = Input(new InstInfo())
     val src_info = Input(new SrcInfo())
-    val result   = Output(UInt(DATA_WID.W))
+    val result   = Output(UInt(XLEN.W))
   })
   val op     = io.info.op
   val src1   = io.src_info.src1_data

chisel/playground/src/pipeline/execute/Csr.scala

@@ -34,7 +34,7 @@ class CsrExecuteUnit(implicit val config: CpuConfig) extends Bundle {
     val ex       = new ExceptionInfo()
   })
   val out = Output(new Bundle {
-    val rdata = UInt(DATA_WID.W)
+    val rdata = UInt(XLEN.W)
     val ex    = new ExceptionInfo()
   })
 }

chisel/playground/src/pipeline/execute/Fu.scala

@@ -16,8 +16,8 @@ class Fu(implicit val config: CpuConfig) extends Module {
         val info     = Input(new InstInfo())
         val src_info = Input(new SrcInfo())
         val result = Output(new Bundle {
-          val mdu = UInt(DATA_WID.W)
+          val mdu = UInt(XLEN.W)
-          val alu = UInt(DATA_WID.W)
+          val alu = UInt(XLEN.W)
         })
       }
     )

chisel/playground/src/pipeline/execute/Mdu.scala

@@ -13,7 +13,7 @@ class Mdu(implicit config: CpuConfig) extends Module {
     val allow_to_go = Input(Bool())
 
     val ready  = Output(Bool())
-    val result = Output(UInt(DATA_WID.W))
+    val result = Output(UInt(XLEN.W))
   })
 
   val mul = Module(new Mul()).io

chisel/playground/src/pipeline/fetch/InstFifo.scala

@@ -7,7 +7,7 @@ import cpu.{BranchPredictorConfig, CpuConfig}
 
 class BufferUnit extends Bundle {
   val bpuConfig = new BranchPredictorConfig()
-  val inst      = UInt(INST_WID.W)
+  val inst      = UInt(XLEN.W)
   val pht_index = UInt(bpuConfig.phtDepth.W)
   val acc_err   = Bool()
   val pc        = UInt(PC_WID.W)

chisel/playground/src/pipeline/memory/DataMemoryAccess.scala

@@ -11,7 +11,7 @@ class DataMemoryAccess_DataMemory extends Bundle {
   val in = Input(new Bundle {
     val acc_err = Bool()
     val ready   = Bool()
-    val rdata   = UInt(DATA_WID.W)
+    val rdata   = UInt(XLEN.W)
   })
   val out = Output(new Bundle {
     val en    = Bool()
@@ -19,7 +19,7 @@ class DataMemoryAccess_DataMemory extends Bundle {
     val wen   = Bool()
     val wstrb = UInt(AXI_STRB_WID.W)
     val addr  = UInt(DATA_ADDR_WID.W)
-    val wdata = UInt(DATA_WID.W)
+    val wdata = UInt(XLEN.W)
   })
 }
 
@@ -37,7 +37,7 @@ class DataMemoryAccess_MemoryUnit extends Bundle {
   })
   val out = Output(new Bundle {
     val ready = Bool()
-    val rdata = UInt(DATA_WID.W)
+    val rdata = UInt(XLEN.W)
     val ex    = new ExceptionInfo()
 
     val set_lr      = Bool()

chisel/playground/src/pipeline/memory/LSExe.scala

@@ -12,7 +12,7 @@ class LSExe extends Module {
     val in = Input(new Bundle {
       val mem_en   = Bool()
       val mem_addr = UInt(DATA_ADDR_WID.W)
-      val wdata    = UInt(DATA_WID.W)
+      val wdata    = UInt(XLEN.W)
       val info     = new InstInfo()
     })
     val out = Output(new Bundle {
@@ -20,7 +20,7 @@ class LSExe extends Module {
       val storeAddrMisaligned = Bool()
       val loadAccessFault     = Bool()
       val storeAccessFault    = Bool()
-      val rdata               = UInt(DATA_WID.W)
+      val rdata               = UInt(XLEN.W)
       val ready               = Bool()
     })
   })