From c0bdc5a097405e532ae6628c0813bae102db0631 Mon Sep 17 00:00:00 2001 From: Liphen Date: Fri, 22 Dec 2023 14:28:13 +0800 Subject: [PATCH] =?UTF-8?q?refactor:=20=E9=83=A8=E5=88=86=E5=B8=B8?= =?UTF-8?q?=E9=87=8F=E6=8D=A2=E6=88=90XLEN?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/cache/DCache.scala | 12 ++++++------ chisel/playground/src/cache/ICache.scala | 8 ++++---- chisel/playground/src/defines/Bundles.scala | 6 +++--- chisel/playground/src/defines/Const.scala | 2 -- .../playground/src/pipeline/decoder/ARegfile.scala | 6 +++--- chisel/playground/src/pipeline/decoder/Decoder.scala | 2 +- chisel/playground/src/pipeline/execute/ALU.scala | 2 +- chisel/playground/src/pipeline/execute/Csr.scala | 2 +- chisel/playground/src/pipeline/execute/Fu.scala | 4 ++-- chisel/playground/src/pipeline/execute/Mdu.scala | 2 +- chisel/playground/src/pipeline/fetch/InstFifo.scala | 2 +- .../src/pipeline/memory/DataMemoryAccess.scala | 6 +++--- chisel/playground/src/pipeline/memory/LSExe.scala | 4 ++-- 13 files changed, 28 insertions(+), 30 deletions(-) diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala index b27777e..fd647a4 100644 --- a/chisel/playground/src/cache/DCache.scala +++ b/chisel/playground/src/cache/DCache.scala @@ -9,7 +9,7 @@ import cpu.CpuConfig import cpu.defines.Const._ class WriteBufferUnit extends Bundle { - val data = UInt(DATA_WID.W) + val data = UInt(XLEN.W) val addr = UInt(DATA_ADDR_WID.W) val strb = UInt(4.W) val size = UInt(2.W) @@ -68,7 +68,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul val working = Bool() })) - val read_buffer = RegInit(VecInit(Seq.fill(16)(0.U(DATA_WID.W)))) + val read_buffer = RegInit(VecInit(Seq.fill(16)(0.U(XLEN.W)))) val ar_handshake = RegInit(false.B) val aw_handshake = RegInit(false.B) @@ -81,7 +81,7 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul val tag_wstrb = RegInit(VecInit(Seq.fill(nway)(false.B))) val tag_wdata = RegInit(0.U(tagWidth.W)) - val data = Wire(Vec(nway, UInt(DATA_WID.W))) + val data = Wire(Vec(nway, UInt(XLEN.W))) val tag = RegInit(VecInit(Seq.fill(nway)(0.U(tagWidth.W)))) val tag_compare_valid = Wire(Vec(nway, Bool())) @@ -103,13 +103,13 @@ class DCache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul ) io.cpu.dcache_ready := !dcache_stall - val saved_rdata = RegInit(0.U(DATA_WID.W)) + val saved_rdata = RegInit(0.U(XLEN.W)) // forward last stored data in data bram val last_waddr = RegNext(data_waddr) - val last_wstrb = RegInit(VecInit(Seq.fill(nway)(0.U(DATA_WID.W)))) + val last_wstrb = RegInit(VecInit(Seq.fill(nway)(0.U(XLEN.W)))) val last_wdata = RegNext(data_wdata) - val cache_data_forward = Wire(Vec(nway, UInt(DATA_WID.W))) + val cache_data_forward = Wire(Vec(nway, UInt(XLEN.W))) io.cpu.rdata := cache_data_forward(sel) diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala index efff650..06f602f 100644 --- a/chisel/playground/src/cache/ICache.scala +++ b/chisel/playground/src/cache/ICache.scala @@ -51,7 +51,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul val instperbank = bankWidth / 4 // 每个bank存储的指令数 val valid = RegInit(VecInit(Seq.fill(nset * nbank)(VecInit(Seq.fill(instperbank)(false.B))))) - val data = Wire(Vec(nway, Vec(instperbank, UInt(DATA_WID.W)))) + val data = Wire(Vec(nway, Vec(instperbank, UInt(XLEN.W)))) val tag = RegInit(VecInit(Seq.fill(nway)(0.U(tagWidth.W)))) // * should choose next addr * // @@ -96,7 +96,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul val inst_valid = VecInit(Seq.tabulate(instperbank)(i => cache_hit_available && i.U <= (3.U - bank_offset))) val saved = RegInit(VecInit(Seq.fill(instperbank)(0.U.asTypeOf(new Bundle { - val inst = UInt(PC_WID.W) + val inst = UInt(INST_WID.W) val valid = Bool() })))) @@ -104,7 +104,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul // bank tag ram for { i <- 0 until nway; j <- 0 until instperbank } { - val bank = Module(new SimpleDualPortRam(nset * nbank, INST_BANK_WID, byteAddressable = true)) + val bank = Module(new SimpleDualPortRam(nset * nbank, INST_WID, byteAddressable = true)) bank.io.ren := true.B bank.io.raddr := data_raddr data(i)(j) := bank.io.rdata @@ -208,7 +208,7 @@ class ICache(cacheConfig: CacheConfig)(implicit config: CpuConfig) extends Modul }.elsewhen(io.axi.r.fire) { // * uncached not support burst transport * // state := s_save - saved(0).inst := io.axi.r.bits.data + saved(0).inst := Mux(ar.addr(2), io.axi.r.bits.data(63, 32), io.axi.r.bits.data(31, 0)) saved(0).valid := true.B rready := false.B acc_err := io.axi.r.bits.resp =/= RESP_OKEY.U diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala index 76818b9..87796c0 100644 --- a/chisel/playground/src/defines/Bundles.scala +++ b/chisel/playground/src/defines/Bundles.scala @@ -39,7 +39,7 @@ class InstInfo extends Bundle { val reg_wen = Bool() val reg_waddr = UInt(REG_ADDR_WID.W) val imm = UInt(XLEN.W) - val inst = UInt(INST_WID.W) + val inst = UInt(XLEN.W) } class MemRead extends Bundle { @@ -109,7 +109,7 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle { val fence = Output(Bool()) // read inst result - val inst = Input(Vec(config.instFetchNum, UInt(INST_WID.W))) + val inst = Input(Vec(config.instFetchNum, UInt(XLEN.W))) val inst_valid = Input(Vec(config.instFetchNum, Bool())) val acc_err = Input(Bool()) val icache_stall = Input(Bool()) // icache_stall @@ -210,5 +210,5 @@ class DEBUG extends Bundle { val wb_pc = Output(UInt(PC_WID.W)) val wb_rf_wen = Output(Bool()) val wb_rf_wnum = Output(UInt(REG_ADDR_WID.W)) - val wb_rf_wdata = Output(UInt(DATA_WID.W)) + val wb_rf_wdata = Output(UInt(XLEN.W)) } diff --git a/chisel/playground/src/defines/Const.scala b/chisel/playground/src/defines/Const.scala index 7ab27e8..f28185f 100644 --- a/chisel/playground/src/defines/Const.scala +++ b/chisel/playground/src/defines/Const.scala @@ -20,7 +20,6 @@ trait Constants extends CoreParameter { val EXC_WID = 16 // inst rom - val INST_BANK_WID = 32 val INST_WID = XLEN val INST_ADDR_WID = XLEN @@ -30,7 +29,6 @@ trait Constants extends CoreParameter { // GPR RegFile val AREG_NUM = 32 val REG_ADDR_WID = 5 - val DATA_WID = XLEN } trait AXIConst { diff --git a/chisel/playground/src/pipeline/decoder/ARegfile.scala b/chisel/playground/src/pipeline/decoder/ARegfile.scala index 2a4ba0d..feaaac5 100644 --- a/chisel/playground/src/pipeline/decoder/ARegfile.scala +++ b/chisel/playground/src/pipeline/decoder/ARegfile.scala @@ -8,7 +8,7 @@ import cpu.CpuConfig class SrcRead extends Bundle { val raddr = Output(UInt(REG_ADDR_WID.W)) - val rdata = Input(UInt(DATA_WID.W)) + val rdata = Input(UInt(XLEN.W)) } class Src12Read extends Bundle { @@ -19,7 +19,7 @@ class Src12Read extends Bundle { class RegWrite extends Bundle { val wen = Output(Bool()) val waddr = Output(UInt(REG_ADDR_WID.W)) - val wdata = Output(UInt(DATA_WID.W)) + val wdata = Output(UInt(XLEN.W)) } class ARegFile(implicit val config: CpuConfig) extends Module { @@ -29,7 +29,7 @@ class ARegFile(implicit val config: CpuConfig) extends Module { }) // 定义32个32位寄存器 - val regs = RegInit(VecInit(Seq.fill(AREG_NUM)(0.U(DATA_WID.W)))) + val regs = RegInit(VecInit(Seq.fill(AREG_NUM)(0.U(XLEN.W)))) // 写寄存器堆 for (i <- 0 until (config.commitNum)) { diff --git a/chisel/playground/src/pipeline/decoder/Decoder.scala b/chisel/playground/src/pipeline/decoder/Decoder.scala index d272160..683c904 100644 --- a/chisel/playground/src/pipeline/decoder/Decoder.scala +++ b/chisel/playground/src/pipeline/decoder/Decoder.scala @@ -9,7 +9,7 @@ class Decoder extends Module with HasInstrType { val io = IO(new Bundle { // inputs val in = Input(new Bundle { - val inst = UInt(INST_WID.W) + val inst = UInt(XLEN.W) }) // outputs val out = Output(new Bundle { diff --git a/chisel/playground/src/pipeline/execute/ALU.scala b/chisel/playground/src/pipeline/execute/ALU.scala index 4492771..27b7bc1 100644 --- a/chisel/playground/src/pipeline/execute/ALU.scala +++ b/chisel/playground/src/pipeline/execute/ALU.scala @@ -9,7 +9,7 @@ class Alu extends Module { val io = IO(new Bundle { val info = Input(new InstInfo()) val src_info = Input(new SrcInfo()) - val result = Output(UInt(DATA_WID.W)) + val result = Output(UInt(XLEN.W)) }) val op = io.info.op val src1 = io.src_info.src1_data diff --git a/chisel/playground/src/pipeline/execute/Csr.scala b/chisel/playground/src/pipeline/execute/Csr.scala index 3c19869..74bdcdb 100644 --- a/chisel/playground/src/pipeline/execute/Csr.scala +++ b/chisel/playground/src/pipeline/execute/Csr.scala @@ -34,7 +34,7 @@ class CsrExecuteUnit(implicit val config: CpuConfig) extends Bundle { val ex = new ExceptionInfo() }) val out = Output(new Bundle { - val rdata = UInt(DATA_WID.W) + val rdata = UInt(XLEN.W) val ex = new ExceptionInfo() }) } diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala index b81017e..aeb2d29 100644 --- a/chisel/playground/src/pipeline/execute/Fu.scala +++ b/chisel/playground/src/pipeline/execute/Fu.scala @@ -16,8 +16,8 @@ class Fu(implicit val config: CpuConfig) extends Module { val info = Input(new InstInfo()) val src_info = Input(new SrcInfo()) val result = Output(new Bundle { - val mdu = UInt(DATA_WID.W) - val alu = UInt(DATA_WID.W) + val mdu = UInt(XLEN.W) + val alu = UInt(XLEN.W) }) } ) diff --git a/chisel/playground/src/pipeline/execute/Mdu.scala b/chisel/playground/src/pipeline/execute/Mdu.scala index 54ad772..eeea066 100644 --- a/chisel/playground/src/pipeline/execute/Mdu.scala +++ b/chisel/playground/src/pipeline/execute/Mdu.scala @@ -13,7 +13,7 @@ class Mdu(implicit config: CpuConfig) extends Module { val allow_to_go = Input(Bool()) val ready = Output(Bool()) - val result = Output(UInt(DATA_WID.W)) + val result = Output(UInt(XLEN.W)) }) val mul = Module(new Mul()).io diff --git a/chisel/playground/src/pipeline/fetch/InstFifo.scala b/chisel/playground/src/pipeline/fetch/InstFifo.scala index 87b5284..7aa9e38 100644 --- a/chisel/playground/src/pipeline/fetch/InstFifo.scala +++ b/chisel/playground/src/pipeline/fetch/InstFifo.scala @@ -7,7 +7,7 @@ import cpu.{BranchPredictorConfig, CpuConfig} class BufferUnit extends Bundle { val bpuConfig = new BranchPredictorConfig() - val inst = UInt(INST_WID.W) + val inst = UInt(XLEN.W) val pht_index = UInt(bpuConfig.phtDepth.W) val acc_err = Bool() val pc = UInt(PC_WID.W) diff --git a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala index afe4c5b..1c4dc50 100644 --- a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala +++ b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala @@ -11,7 +11,7 @@ class DataMemoryAccess_DataMemory extends Bundle { val in = Input(new Bundle { val acc_err = Bool() val ready = Bool() - val rdata = UInt(DATA_WID.W) + val rdata = UInt(XLEN.W) }) val out = Output(new Bundle { val en = Bool() @@ -19,7 +19,7 @@ class DataMemoryAccess_DataMemory extends Bundle { val wen = Bool() val wstrb = UInt(AXI_STRB_WID.W) val addr = UInt(DATA_ADDR_WID.W) - val wdata = UInt(DATA_WID.W) + val wdata = UInt(XLEN.W) }) } @@ -37,7 +37,7 @@ class DataMemoryAccess_MemoryUnit extends Bundle { }) val out = Output(new Bundle { val ready = Bool() - val rdata = UInt(DATA_WID.W) + val rdata = UInt(XLEN.W) val ex = new ExceptionInfo() val set_lr = Bool() diff --git a/chisel/playground/src/pipeline/memory/LSExe.scala b/chisel/playground/src/pipeline/memory/LSExe.scala index e1b3955..13d766d 100644 --- a/chisel/playground/src/pipeline/memory/LSExe.scala +++ b/chisel/playground/src/pipeline/memory/LSExe.scala @@ -12,7 +12,7 @@ class LSExe extends Module { val in = Input(new Bundle { val mem_en = Bool() val mem_addr = UInt(DATA_ADDR_WID.W) - val wdata = UInt(DATA_WID.W) + val wdata = UInt(XLEN.W) val info = new InstInfo() }) val out = Output(new Bundle { @@ -20,7 +20,7 @@ class LSExe extends Module { val storeAddrMisaligned = Bool() val loadAccessFault = Bool() val storeAccessFault = Bool() - val rdata = UInt(DATA_WID.W) + val rdata = UInt(XLEN.W) val ready = Bool() }) })