yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

refactor(exe): alu不会产生例外

This commit is contained in:
Liphen 2023-12-03 14:34:52 +08:00
parent 1952e5f963
commit bda65bef5b
2 changed files with 1 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
View File

@ -57,7 +57,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.info.reg_waddr
io.ctrl.inst(1).mem_wreg := io.executeStage.inst1.info.mem_wreg
io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.info.reg_waddr
io.ctrl.flush := io.fetchUnit.flush
io.ctrl.flush := io.fetchUnit.flush
io.csr.in.valid := is_csr.asUInt.orR
io.csr.in.info := MuxCase(
@ -101,11 +101,9 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
fu.inst(0).pc := io.executeStage.inst0.pc
fu.inst(0).info := io.executeStage.inst0.info
fu.inst(0).src_info := io.executeStage.inst0.src_info
fu.inst(0).ex.in := io.executeStage.inst0.ex
fu.inst(1).pc := io.executeStage.inst1.pc
fu.inst(1).info := io.executeStage.inst1.info
fu.inst(1).src_info := io.executeStage.inst1.src_info
fu.inst(1).ex.in := io.executeStage.inst1.ex
fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch
fu.branch.jump_regiser := io.executeStage.inst0.jb_info.jump_regiser
fu.branch.branch_target := io.executeStage.inst0.jb_info.branch_target
@ -143,8 +141,6 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
io.executeStage.inst0.ex,
MuxLookup(io.executeStage.inst0.info.fusel, io.executeStage.inst0.ex)(
Seq(
FuType.alu -> fu.inst(0).ex.out,
FuType.mdu -> fu.inst(0).ex.out,
FuType.lsu -> accessMemCtrl.inst(0).ex.out,
FuType.csr -> io.csr.out.ex
)
@ -170,8 +166,6 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
io.executeStage.inst1.ex,
MuxLookup(io.executeStage.inst1.info.fusel, io.executeStage.inst1.ex)(
Seq(
FuType.alu -> fu.inst(1).ex.out,
FuType.mdu -> fu.inst(1).ex.out,
FuType.lsu -> accessMemCtrl.inst(1).ex.out,
FuType.csr -> io.csr.out.ex
)

6
chisel/playground/src/pipeline/execute/Fu.scala
View File

@ -15,10 +15,6 @@ class Fu(implicit val config: CpuConfig) extends Module {
val pc = Input(UInt(PC_WID.W))
val info = Input(new InstInfo())
val src_info = Input(new SrcInfo())
val ex = new Bundle {
val in = Input(new ExceptionInfo())
val out = Output(new ExceptionInfo())
}
val result = Output(new Bundle {
val mdu = UInt(DATA_WID.W)
val alu = UInt(DATA_WID.W)
@ -58,8 +54,6 @@ class Fu(implicit val config: CpuConfig) extends Module {
for (i <- 0 until (config.fuNum)) {
alu(i).io.info := io.inst(i).info
alu(i).io.src_info := io.inst(i).src_info
io.inst(i).ex.out := io.inst(i).ex.in
io.inst(i).ex.out.exception := io.inst(i).ex.in.exception
}
io.stall_req := false.B