From bda65bef5baea566d56ed6283647a1a365cd2974 Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Sun, 3 Dec 2023 14:34:52 +0800
Subject: [PATCH] =?UTF-8?q?refactor(exe):=20alu=E4=B8=8D=E4=BC=9A=E4=BA=A7?=
 =?UTF-8?q?=E7=94=9F=E4=BE=8B=E5=A4=96?=
MIME-Version: 1.0
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---
 chisel/playground/src/pipeline/execute/ExecuteUnit.scala | 8 +-------
 chisel/playground/src/pipeline/execute/Fu.scala          | 6 ------
 2 files changed, 1 insertion(+), 13 deletions(-)

diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
index 1e3d7db..7fb2fcf 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
@@ -57,7 +57,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.info.reg_waddr
   io.ctrl.inst(1).mem_wreg  := io.executeStage.inst1.info.mem_wreg
   io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.info.reg_waddr
-  io.ctrl.flush            := io.fetchUnit.flush
+  io.ctrl.flush             := io.fetchUnit.flush
 
   io.csr.in.valid := is_csr.asUInt.orR
   io.csr.in.info := MuxCase(
@@ -101,11 +101,9 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   fu.inst(0).pc           := io.executeStage.inst0.pc
   fu.inst(0).info         := io.executeStage.inst0.info
   fu.inst(0).src_info     := io.executeStage.inst0.src_info
-  fu.inst(0).ex.in        := io.executeStage.inst0.ex
   fu.inst(1).pc           := io.executeStage.inst1.pc
   fu.inst(1).info         := io.executeStage.inst1.info
   fu.inst(1).src_info     := io.executeStage.inst1.src_info
-  fu.inst(1).ex.in        := io.executeStage.inst1.ex
   fu.branch.pred_branch   := io.executeStage.inst0.jb_info.pred_branch
   fu.branch.jump_regiser  := io.executeStage.inst0.jb_info.jump_regiser
   fu.branch.branch_target := io.executeStage.inst0.jb_info.branch_target
@@ -143,8 +141,6 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
     io.executeStage.inst0.ex,
     MuxLookup(io.executeStage.inst0.info.fusel, io.executeStage.inst0.ex)(
       Seq(
-        FuType.alu -> fu.inst(0).ex.out,
-        FuType.mdu -> fu.inst(0).ex.out,
         FuType.lsu -> accessMemCtrl.inst(0).ex.out,
         FuType.csr -> io.csr.out.ex
       )
@@ -170,8 +166,6 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
     io.executeStage.inst1.ex,
     MuxLookup(io.executeStage.inst1.info.fusel, io.executeStage.inst1.ex)(
       Seq(
-        FuType.alu -> fu.inst(1).ex.out,
-        FuType.mdu -> fu.inst(1).ex.out,
         FuType.lsu -> accessMemCtrl.inst(1).ex.out,
         FuType.csr -> io.csr.out.ex
       )
diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala
index 7195a1d..185b4ec 100644
--- a/chisel/playground/src/pipeline/execute/Fu.scala
+++ b/chisel/playground/src/pipeline/execute/Fu.scala
@@ -15,10 +15,6 @@ class Fu(implicit val config: CpuConfig) extends Module {
         val pc       = Input(UInt(PC_WID.W))
         val info     = Input(new InstInfo())
         val src_info = Input(new SrcInfo())
-        val ex = new Bundle {
-          val in  = Input(new ExceptionInfo())
-          val out = Output(new ExceptionInfo())
-        }
         val result = Output(new Bundle {
           val mdu = UInt(DATA_WID.W)
           val alu = UInt(DATA_WID.W)
@@ -58,8 +54,6 @@ class Fu(implicit val config: CpuConfig) extends Module {
   for (i <- 0 until (config.fuNum)) {
     alu(i).io.info              := io.inst(i).info
     alu(i).io.src_info          := io.inst(i).src_info
-    io.inst(i).ex.out           := io.inst(i).ex.in
-    io.inst(i).ex.out.exception := io.inst(i).ex.in.exception
   }
 
   io.stall_req := false.B