yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

增加需要实现的csr

This commit is contained in:
Liphen 2023-11-21 15:10:58 +08:00
parent eecedc6659
commit b75c49177e
9 changed files with 378 additions and 1502 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
chisel/playground/src/Core.scala
View File

@ -18,7 +18,7 @@
// class Core(implicit val config: CpuConfig) extends Module {
// val io = IO(new Bundle {
// val ext_int = Input(UInt(6.W))
// val ext_int = Input(UInt(EXT_INT_WID.W))
// val inst = new Cache_ICache()
// val data = new Cache_DCache()
// val debug = new DEBUG()

2
chisel/playground/src/PuaCpu.scala
View File

@ -7,7 +7,7 @@
// class PuaCpu extends Module {
// implicit val config = new CpuConfig()
// val io = IO(new Bundle {
// val ext_int = Input(UInt(6.W))
// val ext_int = Input(UInt(EXT_INT_WID.W))
// val axi = new AXI()
// val debug = new DEBUG()
// })

1
chisel/playground/src/defines/Const.scala
View File

@ -17,6 +17,7 @@ trait Constants extends CoreParameter {
val SINGLE_ISSUE = false.B
val DUAL_ISSUE = true.B
val EXT_INT_WID = 3
val INT_WID = 12
val EXCODE_WID = 16

128
chisel/playground/src/defines/Cp0Bundles.scala
View File

@ -1,128 +0,0 @@
// package cpu.defines
// import chisel3._
// import chisel3.util._
// import cpu.defines.Const._
// class CsrIndex extends Bundle {
// val p = Bool()
// val blank = UInt((32 - 1 - log2Ceil(TLB_NUM)).W)
// val index = UInt(log2Ceil(TLB_NUM).W)
// }
// class CsrRandom extends Bundle {
// val blank = UInt((32 - log2Ceil(TLB_NUM)).W)
// val random = UInt(log2Ceil(TLB_NUM).W)
// }
// class CsrEntryLo extends Bundle {
// val fill = UInt((32 - PFN_WID - C_WID - 3).W)
// val pfn = UInt(PFN_WID.W)
// val c = UInt(C_WID.W)
// val d = Bool()
// val v = Bool()
// val g = Bool()
// }
// class CsrContext extends Bundle {
// val ptebase = UInt(PTEBASE_WID.W)
// val badvpn2 = UInt(VPN2_WID.W)
// val blank = UInt((32 - PTEBASE_WID - VPN2_WID).W)
// }
// class CsrWired extends Bundle {
// val blank = UInt((31 - log2Ceil(TLB_NUM)).W)
// val wired = UInt(log2Ceil(TLB_NUM).W)
// }
// class CsrBadVAddr extends Bundle {
// val badvaddr = UInt(PC_WID.W)
// }
// class CsrCount extends Bundle {
// val count = UInt(DATA_WID.W)
// }
// class CsrEntryHi extends Bundle {
// val vpn2 = UInt(VPN2_WID.W)
// val blank = UInt((32 - VPN2_WID - ASID_WID).W)
// val asid = UInt(ASID_WID.W)
// }
// class CsrCompare extends Bundle {
// val compare = UInt(DATA_WID.W)
// }
// class CsrStatus extends Bundle {
// val blank3 = UInt(3.W)
// val cu0 = Bool()
// val blank2 = UInt(5.W)
// val bev = Bool()
// val blank1 = UInt(6.W)
// val im = UInt(8.W)
// val blank0 = UInt(3.W)
// val um = Bool()
// val r0 = Bool()
// val erl = Bool()
// val exl = Bool()
// val ie = Bool()
// }
// class CsrCause extends Bundle {
// val bd = Bool()
// val blank3 = UInt(7.W)
// val iv = Bool()
// val blank2 = UInt(7.W)
// val ip = UInt(8.W)
// val blank1 = Bool()
// val excode = UInt(5.W)
// val blank0 = UInt(2.W)
// }
// class CsrEpc extends Bundle {
// val epc = UInt(PC_WID.W)
// }
// class CsrEbase extends Bundle {
// val fill = Bool()
// val blank1 = Bool()
// val ebase = UInt(18.W)
// val blank0 = UInt(2.W)
// val cpuNum = UInt(10.W)
// }
// class CsrConfig extends Bundle {
// val m = Bool()
// val k23 = UInt(3.W)
// val ku = UInt(3.W)
// val impl = UInt(9.W)
// val be = Bool()
// val at = UInt(2.W)
// val ar = UInt(3.W)
// val mt = UInt(3.W)
// val blank = UInt(3.W)
// val vi = Bool()
// val k0 = UInt(3.W)
// }
// class CsrConfig1 extends Bundle {
// val m = Bool()
// val ms = UInt(6.W)
// val is = UInt(3.W)
// val il = UInt(3.W)
// val ia = UInt(3.W)
// val ds = UInt(3.W)
// val dl = UInt(3.W)
// val da = UInt(3.W)
// val c2 = Bool()
// val md = Bool()
// val pc = Bool()
// val wr = Bool()
// val ca = Bool()
// val ep = Bool()
// val fp = Bool()
// }
// class CsrErrorEpc extends Bundle {
// val errorEpc = UInt(PC_WID.W)
// }

90
chisel/playground/src/defines/CsrBundles.scala Normal file
View File

@ -0,0 +1,90 @@
package cpu.defines
import chisel3._
import chisel3.util._
import cpu.defines.Const._
class Mstatus extends Bundle {
val sd = Bool()
val wpri0 = UInt(25.W)
val mbe = Bool()
val sbe = Bool()
val sxl = UInt(2.W)
val uxl = UInt(2.W)
val wpri1 = UInt(9.W)
val tsr = Bool()
val tw = Bool()
val tvm = Bool()
val mxr = Bool()
val sum = Bool()
val mprv = Bool()
val xs = UInt(2.W)
val fs = UInt(2.W)
val mpp = UInt(2.W)
val vs = UInt(2.W)
val spp = Bool()
val mpie = Bool()
val ube = Bool()
val spie = Bool()
val wpri2 = Bool()
val mie = Bool()
val wpri3 = Bool()
val sie = Bool()
val wpri4 = Bool()
}
class Misa extends Bundle {
val mxl = UInt(2.W)
val blank = UInt((XLEN - 28).W)
val extensions = UInt(26.W)
}
class Mtvec extends Bundle {
val base = UInt((XLEN - 2).W)
val mode = UInt(2.W)
}
class Mcause extends Bundle {
val interrupt = Bool()
val excode = UInt((XLEN - 1).W)
}
class Mip extends Bundle {
val blank0 = UInt(52.W)
val meip = Bool()
val blank1 = UInt(2.W)
val seip = Bool()
val blank2 = UInt(2.W)
val mtip = Bool()
val blank3 = UInt(2.W)
val stip = Bool()
val blank4 = UInt(2.W)
val msip = Bool()
val blank5 = UInt(2.W)
val ssip = Bool()
val blank6 = UInt(2.W)
}
class Mie extends Bundle {
val blank0 = UInt(52.W)
val meie = Bool()
val blank1 = UInt(2.W)
val seie = Bool()
val blank2 = UInt(2.W)
val mtie = Bool()
val blank3 = UInt(2.W)
val stie = Bool()
val blank4 = UInt(2.W)
val msie = Bool()
val blank5 = UInt(2.W)
val ssie = Bool()
val blank6 = UInt(2.W)
}
object Priv {
def u = "b00".U
def s = "b01".U
def h = "b10".U
def m = "b11".U
def apply() = UInt(2.W)
}

1028
chisel/playground/src/defines/isa/Instructions.scala
View File

File diff suppressed because it is too large Load Diff

440
chisel/playground/src/pipeline/execute/Csr.scala
View File

@ -1,368 +1,88 @@
// package cpu.pipeline.execute
package cpu.pipeline.execute
// import chisel3._
// import chisel3.util._
// import cpu.defines._
// import cpu.defines.Const._
// import cpu.pipeline.memory.CsrInfo
// import cpu.CpuConfig
// import cpu.pipeline.decoder.CsrDecoderUnit
import chisel3._
import chisel3.util._
import cpu.defines._
import cpu.defines.Const._
import cpu.pipeline.memory.CsrInfo
import cpu.CpuConfig
import cpu.pipeline.decoder.CsrDecoderUnit
// class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
// val in = Input(new Bundle {
// val inst = Vec(
// config.fuNum,
// new Bundle {
// val pc = UInt(PC_WID.W)
// val ex = new ExceptionInfo()
// }
// )
// })
// val out = Output(new Bundle {
// val flush = Bool()
// val flush_pc = UInt(PC_WID.W)
// })
// }
class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
val in = Input(new Bundle {
val inst = Vec(
config.fuNum,
new Bundle {
val pc = UInt(PC_WID.W)
val ex = new ExceptionInfo()
}
)
})
val out = Output(new Bundle {
val flush = Bool()
val flush_pc = UInt(PC_WID.W)
})
}
// class CsrExecuteUnit(implicit val config: CpuConfig) extends Bundle {
// val in = Input(new Bundle {
// val inst_info = Vec(config.fuNum, new InstInfo())
// val mtc0_wdata = UInt(DATA_WID.W)
// })
// val out = Output(new Bundle {
// val csr_rdata = Vec(config.fuNum, UInt(DATA_WID.W))
// val debug = Output(new CsrInfo())
// })
// }
class CsrExecuteUnit(implicit val config: CpuConfig) extends Bundle {
val in = Input(new Bundle {
val inst_info = Vec(config.fuNum, new InstInfo())
val mtc0_wdata = UInt(DATA_WID.W)
})
val out = Output(new Bundle {
val csr_rdata = Vec(config.fuNum, UInt(DATA_WID.W))
val debug = Output(new CsrInfo())
})
}
// class Csr(implicit val config: CpuConfig) extends Module {
// val io = IO(new Bundle {
// val ext_int = Input(UInt(EXT_INT_WID.W))
// val ctrl = Input(new Bundle {
// val exe_stall = Bool()
// val mem_stall = Bool()
// })
// val decoderUnit = Output(new CsrDecoderUnit())
// val executeUnit = new CsrExecuteUnit()
// val memoryUnit = new CsrMemoryUnit()
// })
// // 优先使用inst0的信息
// val ex_sel = io.memoryUnit.in.inst(0).ex.flush_req || !io.memoryUnit.in.inst(1).ex.flush_req
// val pc = Mux(ex_sel, io.memoryUnit.in.inst(0).pc, io.memoryUnit.in.inst(1).pc)
// val ex = Mux(ex_sel, io.memoryUnit.in.inst(0).ex, io.memoryUnit.in.inst(1).ex)
// val mtc0_wen = io.executeUnit.in.inst_info(0).op === EXE_MTC0
// val mtc0_wdata = io.executeUnit.in.mtc0_wdata
// val mtc0_addr = io.executeUnit.in.inst_info(0).csr_addr
// val exe_op = io.executeUnit.in.inst_info(0).op
// val exe_stall = io.ctrl.exe_stall
// val mem_stall = io.ctrl.mem_stall
class Csr(implicit val config: CpuConfig) extends Module {
val io = IO(new Bundle {
val ext_int = Input(UInt(EXT_INT_WID.W))
val ctrl = Input(new Bundle {
val exe_stall = Bool()
val mem_stall = Bool()
})
val decoderUnit = Output(new CsrDecoderUnit())
val executeUnit = new CsrExecuteUnit()
val memoryUnit = new CsrMemoryUnit()
})
// 优先使用inst0的信息
val ex_sel = io.memoryUnit.in.inst(0).ex.flush_req || !io.memoryUnit.in.inst(1).ex.flush_req
val pc = Mux(ex_sel, io.memoryUnit.in.inst(0).pc, io.memoryUnit.in.inst(1).pc)
val ex = Mux(ex_sel, io.memoryUnit.in.inst(0).ex, io.memoryUnit.in.inst(1).ex)
val exe_op = io.executeUnit.in.inst_info(0).op
val exe_stall = io.ctrl.exe_stall
val mem_stall = io.ctrl.mem_stall
// // ---------------csr-defines-----------------
val cycle = RegInit(0.U(XLEN.W)) // 时钟周期计数器
// // index register (0,0)
// val csr_index = RegInit(0.U.asTypeOf(new CsrIndex()))
val instret = RegInit(0.U(XLEN.W)) // 指令计数器
// // random register (1,0)
// val random_init = Wire(new CsrRandom())
// random_init := 0.U.asTypeOf(new CsrRandom())
// random_init.random := (TLB_NUM - 1).U
// val csr_random = RegInit(random_init)
val mvendorid = RegInit(0.U(XLEN.W)) // 厂商ID
val marchid = RegInit(0.U(XLEN.W)) // 架构ID
val mimpid = RegInit(0.U(XLEN.W)) // 实现ID
val mhartid = RegInit(0.U(XLEN.W)) // 硬件线程ID
val mconfigptr = RegInit(0.U(XLEN.W)) // 配置寄存器指针
val mstatus_init = Wire(new Mstatus())
mstatus_init := 0.U.asTypeOf(new Mstatus())
mstatus_init.uxl := 2.U
val mstatus = RegInit(mstatus_init) // 状态寄存器
val misa_init = Wire(new Misa())
misa_init := 0.U.asTypeOf(new Misa())
misa_init.mxl := 2.U
misa_init.extensions := "h101100".U
val misa = RegInit(misa_init) // ISA寄存器
val mie = RegInit(0.U.asTypeOf(new Mie())) // 中断使能寄存器
val mtvec = RegInit(0.U.asTypeOf(new Mtvec())) // 中断向量基址寄存器
val mcounteren = RegInit(0.U(XLEN.W)) // 计数器使能寄存器
val mscratch = RegInit(0.U(XLEN.W)) // 临时寄存器
val mepc = RegInit(0.U(XLEN.W)) // 异常程序计数器
val mcause = RegInit(0.U.asTypeOf(new Mcause())) // 异常原因寄存器
val mtval = RegInit(0.U(XLEN.W)) // 异常值寄存器
val mip = RegInit(0.U.asTypeOf(new Mip())) // 中断挂起寄存器
val mcycle = cycle // 时钟周期计数器
val minstret = instret // 指令计数器
// // entrylo0 register (2,0)
// val csr_entrylo0 = RegInit(0.U.asTypeOf(new CsrEntryLo()))
// // entrylo1 register (3,0)
// val csr_entrylo1 = RegInit(0.U.asTypeOf(new CsrEntryLo()))
// // context register (4,0)
// val csr_context = RegInit(0.U.asTypeOf(new CsrContext()))
// // page mask register (5,0)
// val csr_pagemask = 0.U
// // wired register (6,0)
// val csr_wired = RegInit(0.U.asTypeOf(new CsrWired()))
// // badvaddr register (8,0)
// val csr_badvaddr = RegInit(0.U.asTypeOf(new CsrBadVAddr()))
// // count register (9,0)
// val count_init = Wire(new CsrCount())
// count_init := 0.U.asTypeOf(new CsrCount())
// count_init.count := 1.U
// val csr_count = RegInit(count_init)
// // entryhi register (10,0)
// val csr_entryhi = RegInit(0.U.asTypeOf(new CsrEntryHi()))
// // compare register (11,0)
// val csr_compare = RegInit(0.U.asTypeOf(new CsrCompare()))
// // status register (12,0)
// val status_init = Wire(new CsrStatus())
// status_init := 0.U.asTypeOf(new CsrStatus())
// status_init.bev := true.B
// val csr_status = RegInit(status_init)
// // cause register (13,0)
// val csr_cause = RegInit(0.U.asTypeOf(new CsrCause()))
// // epc register (14,0)
// val csr_epc = RegInit(0.U.asTypeOf(new CsrEpc()))
// // prid register (15,0)
// val prid = "h_0001_8003".U
// // ebase register (15,1)
// val ebase_init = Wire(new CsrEbase())
// ebase_init := 0.U.asTypeOf(new CsrEbase())
// ebase_init.fill := true.B
// val csr_ebase = RegInit(ebase_init)
// // config register (16,0)
// val csr_config = Wire(new CsrConfig())
// csr_config := 0.U.asTypeOf(new CsrConfig())
// csr_config.k0 := 3.U
// csr_config.mt := 1.U
// csr_config.m := true.B
// // config1 register (16,1)
// val csr_config1 = Wire(new CsrConfig1())
// csr_config1 := 0.U.asTypeOf(new CsrConfig1())
// csr_config1.il := 5.U
// csr_config1.ia := 1.U
// csr_config1.dl := 5.U
// csr_config1.da := 1.U
// csr_config1.ms := (TLB_NUM - 1).U
// // taglo register (28,0)
// val csr_taglo = RegInit(0.U(DATA_WID.W))
// // taghi register (29,0)
// val csr_taghi = RegInit(0.U(DATA_WID.W))
// // error epc register (30,0)
// val csr_error_epc = RegInit(0.U.asTypeOf(new CsrEpc()))
// // random register (1,0)
// csr_random.random := Mux(csr_random.random === csr_wired.wired, (TLB_NUM - 1).U, (csr_random.random - 1.U))
// // context register (4,0)
// when(!mem_stall && ex.flush_req) {
// when(VecInit(EX_TLBL, EX_TLBS, EX_MOD).contains(ex.excode)) {
// csr_context.badvpn2 := ex.badvaddr(31, 13)
// }
// }.elsewhen(!exe_stall) {
// when(mtc0_wen && mtc0_addr === CSR_CONTEXT_ADDR) {
// csr_context.ptebase := mtc0_wdata.asTypeOf(new CsrContext()).ptebase
// }
// }
// // wired register (6,0)
// when(!exe_stall) {
// when(mtc0_wen && mtc0_addr === CSR_WIRED_ADDR) {
// csr_wired.wired := mtc0_wdata.asTypeOf(new CsrWired()).wired
// csr_random.random := (TLB_NUM - 1).U
// }
// }
// // badvaddr register (8,0)
// when(!mem_stall && ex.flush_req) {
// when(VecInit(EX_ADEL, EX_TLBL, EX_ADES, EX_TLBS, EX_MOD).contains(ex.excode)) {
// csr_badvaddr.badvaddr := ex.badvaddr
// }
// }
// // count register (9,0)
// val tick = RegInit(false.B)
// tick := !tick
// when(tick) {
// csr_count.count := csr_count.count + 1.U
// }
// when(!exe_stall) {
// when(mtc0_wen && mtc0_addr === CSR_COUNT_ADDR) {
// csr_count.count := mtc0_wdata.asTypeOf(new CsrCount()).count
// }
// }
// // entryhi register (10,0)
// when(!mem_stall && ex.flush_req) {
// when(VecInit(EX_TLBL, EX_TLBS, EX_MOD).contains(ex.excode)) {
// csr_entryhi.vpn2 := ex.badvaddr(31, 13)
// }
// }.elsewhen(!exe_stall) {
// when(mtc0_wen && mtc0_addr === CSR_ENTRYHI_ADDR) {
// val wdata = mtc0_wdata.asTypeOf(new CsrEntryHi())
// csr_entryhi.asid := wdata.asid
// csr_entryhi.vpn2 := wdata.vpn2
// }
// }
// // compare register (11,0)
// when(!exe_stall) {
// when(mtc0_wen && mtc0_addr === CSR_COMPARE_ADDR) {
// csr_compare.compare := mtc0_wdata.asTypeOf(new CsrCompare()).compare
// }
// }
// // status register (12,0)
// when(!mem_stall && ex.eret) {
// when(csr_status.erl) {
// csr_status.erl := false.B
// }.otherwise {
// csr_status.exl := false.B
// }
// }.elsewhen(!mem_stall && ex.flush_req) {
// csr_status.exl := true.B
// }.elsewhen(!exe_stall) {
// when(mtc0_wen && mtc0_addr === CSR_STATUS_ADDR) {
// val wdata = mtc0_wdata.asTypeOf(new CsrStatus())
// csr_status.cu0 := wdata.cu0
// csr_status.ie := wdata.ie
// csr_status.exl := wdata.exl
// csr_status.erl := wdata.erl
// csr_status.um := wdata.um
// csr_status.im := wdata.im
// csr_status.bev := wdata.bev
// }
// }
// // cause register (13,0)
// csr_cause.ip := Cat(
// csr_cause.ip(7) || csr_compare.compare === csr_count.count || io.ext_int(5), // TODO:此处的ext_int可能不对
// io.ext_int(4, 0),
// csr_cause.ip(1, 0)
// )
// when(!mem_stall && ex.flush_req && !ex.eret) {
// when(!csr_status.exl) {
// csr_cause.bd := ex.bd
// }
// csr_cause.excode := MuxLookup(ex.excode, csr_cause.excode)(
// Seq(
// EX_NO -> EXC_NO,
// EX_INT -> EXC_INT,
// EX_MOD -> EXC_MOD,
// EX_TLBL -> EXC_TLBL,
// EX_TLBS -> EXC_TLBS,
// EX_ADEL -> EXC_ADEL,
// EX_ADES -> EXC_ADES,
// EX_SYS -> EXC_SYS,
// EX_BP -> EXC_BP,
// EX_RI -> EXC_RI,
// EX_CPU -> EXC_CPU,
// EX_OV -> EXC_OV
// )
// )
// }.elsewhen(!exe_stall) {
// when(mtc0_wen) {
// when(mtc0_addr === CSR_COMPARE_ADDR) {
// csr_cause.ip := Cat(false.B, csr_cause.ip(6, 0))
// }.elsewhen(mtc0_addr === CSR_CAUSE_ADDR) {
// val wdata = mtc0_wdata.asTypeOf(new CsrCause())
// csr_cause.ip := Cat(
// csr_cause.ip(7, 2),
// wdata.ip(1, 0)
// )
// csr_cause.iv := wdata.iv
// }
// }
// }
// // epc register (14,0)
// when(!mem_stall && ex.flush_req) {
// when(!csr_status.exl) {
// csr_epc.epc := Mux(ex.bd, pc - 4.U, pc)
// }
// }.elsewhen(!exe_stall) {
// when(mtc0_wen && mtc0_addr === CSR_EPC_ADDR) {
// csr_epc.epc := mtc0_wdata.asTypeOf(new CsrEpc()).epc
// }
// }
// // ebase register (15,1)
// when(!exe_stall) {
// when(mtc0_wen && mtc0_addr === CSR_EBASE_ADDR) {
// csr_ebase.ebase := mtc0_wdata.asTypeOf(new CsrEbase()).ebase
// }
// }
// // taglo register (28,0)
// when(!exe_stall) {
// when(mtc0_wen && mtc0_addr === CSR_TAGLO_ADDR) {
// csr_taglo := mtc0_wdata
// }
// }
// // taghi register (29,0)
// when(!exe_stall) {
// when(mtc0_wen && mtc0_addr === CSR_TAGHI_ADDR) {
// csr_taghi := mtc0_wdata
// }
// }
// // error epc register (30,0)
// when(!exe_stall) {
// when(mtc0_wen && mtc0_addr === CSR_ERROR_EPC_ADDR) {
// csr_error_epc.epc := mtc0_wdata.asTypeOf(new CsrEpc()).epc
// }
// }
// for (i <- 0 until config.fuNum) {
// io.executeUnit.out.csr_rdata(i) := MuxLookup(io.executeUnit.in.inst_info(i).csr_addr, 0.U)(
// Seq(
// CSR_INDEX_ADDR -> csr_index.asUInt,
// CSR_RANDOM_ADDR -> csr_random.asUInt,
// CSR_ENTRYLO0_ADDR -> csr_entrylo0.asUInt,
// CSR_ENTRYLO1_ADDR -> csr_entrylo1.asUInt,
// CSR_CONTEXT_ADDR -> csr_context.asUInt,
// CSR_PAGE_MASK_ADDR -> csr_pagemask,
// CSR_WIRED_ADDR -> csr_wired.asUInt,
// CSR_BADV_ADDR -> csr_badvaddr.asUInt,
// CSR_COUNT_ADDR -> csr_count.asUInt,
// CSR_ENTRYHI_ADDR -> csr_entryhi.asUInt,
// CSR_COMPARE_ADDR -> csr_compare.asUInt,
// CSR_STATUS_ADDR -> csr_status.asUInt,
// CSR_CAUSE_ADDR -> csr_cause.asUInt,
// CSR_EPC_ADDR -> csr_epc.asUInt,
// CSR_PRID_ADDR -> prid,
// CSR_EBASE_ADDR -> csr_ebase.asUInt,
// CSR_CONFIG_ADDR -> csr_config.asUInt,
// CSR_CONFIG1_ADDR -> csr_config1.asUInt,
// CSR_TAGLO_ADDR -> csr_taglo,
// CSR_TAGHI_ADDR -> csr_taghi,
// CSR_ERROR_EPC_ADDR -> csr_error_epc.asUInt
// )
// )
// }
// io.decoderUnit.cause_ip := csr_cause.ip
// io.decoderUnit.status_im := csr_status.im
// io.decoderUnit.kernel_mode := (csr_status.exl && !(ex.eret && csr_status.erl)) ||
// (csr_status.erl && !ex.eret) ||
// !csr_status.um ||
// (ex.flush_req && !ex.eret)
// io.decoderUnit.access_allowed := io.decoderUnit.kernel_mode || csr_status.cu0
// io.decoderUnit.intterupt_allowed := csr_status.ie && !csr_status.exl && !csr_status.erl
// io.executeUnit.out.debug.csr_cause := csr_cause.asUInt
// io.executeUnit.out.debug.csr_count := csr_count.asUInt
// io.executeUnit.out.debug.csr_random := csr_random.asUInt
// val trap_base = Mux(
// csr_status.bev,
// "hbfc00200".U(PC_WID.W),
// csr_ebase.asUInt
// )
// io.memoryUnit.out.flush := false.B
// io.memoryUnit.out.flush_pc := 0.U
// when(ex.eret) {
// io.memoryUnit.out.flush := true.B && !io.ctrl.mem_stall
// io.memoryUnit.out.flush_pc := Mux(csr_status.erl, csr_error_epc.epc, csr_epc.epc)
// }.elsewhen(ex.flush_req) {
// io.memoryUnit.out.flush := true.B && !io.ctrl.mem_stall
// io.memoryUnit.out.flush_pc := Mux(
// csr_status.exl,
// trap_base + "h180".U,
// trap_base + "h200".U
// )
// }
// }
val tselect = RegInit(1.U(XLEN.W)) // 跟踪寄存器选择寄存器
val tdata1 = RegInit(0.U(XLEN.W)) // 跟踪寄存器数据1寄存器
}

2
chisel/playground/src/pipeline/execute/ExecuteUnit.scala
View File

@ -94,7 +94,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
Seq(
(fu.branch.pred_fail && fu.branch.branch) -> io.executeStage.inst0.jb_info.branch_target,
(fu.branch.pred_fail && !fu.branch.branch) -> (io.executeStage.inst0.pc + 4.U),
(io.executeStage.inst0.jb_info.jump_regiser) -> io.executeStage.inst0.src_info.src1_data
(io.executeStage.inst0.jb_info.jump_regiser) -> (io.executeStage.inst0.src_info.src1_data + io.executeStage.inst0.src_info.src2_data)
)
)

179
chisel/playground/src/pipeline/memory/MemoryUnit.scala
View File

@ -1,103 +1,94 @@
// package cpu.pipeline.memory
package cpu.pipeline.memory
// import chisel3._
// import chisel3.util._
// import cpu.defines._
// import cpu.defines.Const._
// import cpu.CpuConfig
// import cpu.pipeline.decoder.RegWrite
// import cpu.pipeline.execute.CsrMemoryUnit
// import cpu.pipeline.writeback.MemoryUnitWriteBackUnit
import chisel3._
import chisel3.util._
import cpu.defines._
import cpu.defines.Const._
import cpu.CpuConfig
import cpu.pipeline.decoder.RegWrite
import cpu.pipeline.execute.CsrMemoryUnit
import cpu.pipeline.writeback.MemoryUnitWriteBackUnit
// class MemoryUnit(implicit val config: CpuConfig) extends Module {
// val io = IO(new Bundle {
// val ctrl = new MemoryCtrl()
// val memoryStage = Input(new ExecuteUnitMemoryUnit())
// val fetchUnit = Output(new Bundle {
// val flush = Bool()
// val flush_pc = UInt(PC_WID.W)
// })
// val decoderUnit = Output(Vec(config.fuNum, new RegWrite()))
// val csr = Flipped(new CsrMemoryUnit())
// val writeBackStage = Output(new MemoryUnitWriteBackUnit())
// val dataMemory = new Bundle {
// val in = Input(new Bundle {
// val rdata = UInt(DATA_WID.W)
// })
// val out = Output(new Bundle {
// val en = Bool()
// val rlen = UInt(2.W)
// val wen = UInt(4.W)
// val addr = UInt(DATA_ADDR_WID.W)
// val wdata = UInt(DATA_WID.W)
// })
// }
// })
class MemoryUnit(implicit val config: CpuConfig) extends Module {
val io = IO(new Bundle {
val ctrl = new MemoryCtrl()
val memoryStage = Input(new ExecuteUnitMemoryUnit())
val fetchUnit = Output(new Bundle {
val flush = Bool()
val flush_pc = UInt(PC_WID.W)
})
val decoderUnit = Output(Vec(config.fuNum, new RegWrite()))
val csr = Flipped(new CsrMemoryUnit())
val writeBackStage = Output(new MemoryUnitWriteBackUnit())
val dataMemory = new Bundle {
val in = Input(new Bundle {
val rdata = UInt(DATA_WID.W)
})
val out = Output(new Bundle {
val en = Bool()
val rlen = UInt(2.W)
val wen = UInt(4.W)
val addr = UInt(DATA_ADDR_WID.W)
val wdata = UInt(DATA_WID.W)
})
}
})
// val dataMemoryAccess = Module(new DataMemoryAccess()).io
// dataMemoryAccess.memoryUnit.in.mem_en := io.memoryStage.inst0.mem.en
// dataMemoryAccess.memoryUnit.in.inst_info := io.memoryStage.inst0.mem.inst_info
// dataMemoryAccess.memoryUnit.in.mem_wdata := io.memoryStage.inst0.mem.wdata
// dataMemoryAccess.memoryUnit.in.mem_addr := io.memoryStage.inst0.mem.addr
// dataMemoryAccess.memoryUnit.in.mem_sel := io.memoryStage.inst0.mem.sel
// dataMemoryAccess.memoryUnit.in.ex(0) := io.memoryStage.inst0.ex
// dataMemoryAccess.memoryUnit.in.ex(1) := io.memoryStage.inst1.ex
// dataMemoryAccess.dataMemory.in.rdata := io.dataMemory.in.rdata
// dataMemoryAccess.memoryUnit.in.llbit := io.memoryStage.inst0.mem.llbit
// io.dataMemory.out := dataMemoryAccess.dataMemory.out
val dataMemoryAccess = Module(new DataMemoryAccess()).io
dataMemoryAccess.memoryUnit.in.mem_en := io.memoryStage.inst0.mem.en
dataMemoryAccess.memoryUnit.in.inst_info := io.memoryStage.inst0.mem.inst_info
dataMemoryAccess.memoryUnit.in.mem_wdata := io.memoryStage.inst0.mem.wdata
dataMemoryAccess.memoryUnit.in.mem_addr := io.memoryStage.inst0.mem.addr
dataMemoryAccess.memoryUnit.in.mem_sel := io.memoryStage.inst0.mem.sel
dataMemoryAccess.memoryUnit.in.ex(0) := io.memoryStage.inst0.ex
dataMemoryAccess.memoryUnit.in.ex(1) := io.memoryStage.inst1.ex
dataMemoryAccess.dataMemory.in.rdata := io.dataMemory.in.rdata
io.dataMemory.out := dataMemoryAccess.dataMemory.out
// io.decoderUnit(0).wen := io.writeBackStage.inst0.inst_info.reg_wen
// io.decoderUnit(0).waddr := io.writeBackStage.inst0.inst_info.reg_waddr
// io.decoderUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata
// io.decoderUnit(1).wen := io.writeBackStage.inst1.inst_info.reg_wen
// io.decoderUnit(1).waddr := io.writeBackStage.inst1.inst_info.reg_waddr
// io.decoderUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata
io.decoderUnit(0).wen := io.writeBackStage.inst0.inst_info.reg_wen
io.decoderUnit(0).waddr := io.writeBackStage.inst0.inst_info.reg_waddr
io.decoderUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata
io.decoderUnit(1).wen := io.writeBackStage.inst1.inst_info.reg_wen
io.decoderUnit(1).waddr := io.writeBackStage.inst1.inst_info.reg_waddr
io.decoderUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata
// io.writeBackStage.inst0.pc := io.memoryStage.inst0.pc
// io.writeBackStage.inst0.inst_info := io.memoryStage.inst0.inst_info
// io.writeBackStage.inst0.rd_info.wdata := Mux(
// io.writeBackStage.inst0.inst_info.mem_wreg,
// dataMemoryAccess.memoryUnit.out.rdata,
// io.memoryStage.inst0.rd_info.wdata,
// )
// io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex
// io.writeBackStage.inst0.ex.excode := MuxCase(
// io.memoryStage.inst0.ex.excode,
// Seq(
// (io.memoryStage.inst0.ex.excode =/= EX_NO) -> io.memoryStage.inst0.ex.excode,
// ),
// )
// io.writeBackStage.inst0.ex.flush_req := io.memoryStage.inst0.ex.flush_req || io.writeBackStage.inst0.ex.excode =/= EX_NO
// io.writeBackStage.inst0.csr := io.memoryStage.inst0.csr
io.writeBackStage.inst0.pc := io.memoryStage.inst0.pc
io.writeBackStage.inst0.inst_info := io.memoryStage.inst0.inst_info
io.writeBackStage.inst0.rd_info.wdata := Mux(
io.writeBackStage.inst0.inst_info.mem_wreg,
dataMemoryAccess.memoryUnit.out.rdata,
io.memoryStage.inst0.rd_info.wdata
)
io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex
io.writeBackStage.inst0.ex.excode := io.memoryStage.inst0.ex.excode
// io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc
// io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info
// io.writeBackStage.inst1.rd_info.wdata := Mux(
// io.writeBackStage.inst1.inst_info.mem_wreg,
// dataMemoryAccess.memoryUnit.out.rdata,
// io.memoryStage.inst1.rd_info.wdata,
// )
// io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex
// io.writeBackStage.inst1.ex.excode := MuxCase(
// io.memoryStage.inst1.ex.excode,
// Seq(
// (io.memoryStage.inst1.ex.excode =/= EX_NO) -> io.memoryStage.inst1.ex.excode,
// ),
// )
// io.writeBackStage.inst1.ex.flush_req := io.memoryStage.inst1.ex.flush_req || io.writeBackStage.inst1.ex.excode =/= EX_NO
io.writeBackStage.inst0.ex.flush_req := io.memoryStage.inst0.ex.flush_req || io.writeBackStage.inst0.ex.excode.asUInt.orR
io.writeBackStage.inst0.csr := io.memoryStage.inst0.csr
// io.csr.in.inst(0).pc := io.writeBackStage.inst0.pc
// io.csr.in.inst(0).ex := io.writeBackStage.inst0.ex
// io.csr.in.inst(1).pc := io.writeBackStage.inst1.pc
// io.csr.in.inst(1).ex := io.writeBackStage.inst1.ex
io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc
io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info
io.writeBackStage.inst1.rd_info.wdata := Mux(
io.writeBackStage.inst1.inst_info.mem_wreg,
dataMemoryAccess.memoryUnit.out.rdata,
io.memoryStage.inst1.rd_info.wdata
)
io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex
io.writeBackStage.inst1.ex.excode := io.memoryStage.inst1.ex.excode
// io.fetchUnit.flush := Mux(
// io.csr.out.flush,
// io.csr.out.flush,
// io.writeBackStage.inst0.inst_info.op === EXE_MTC0 && io.ctrl.allow_to_go,
// )
// io.fetchUnit.flush_pc := Mux(io.csr.out.flush, io.csr.out.flush_pc, io.writeBackStage.inst0.pc + 4.U)
io.writeBackStage.inst1.ex.flush_req := io.memoryStage.inst1.ex.flush_req || io.writeBackStage.inst1.ex.excode.asUInt.orR
// io.ctrl.flush_req := io.fetchUnit.flush
// io.ctrl.eret := io.writeBackStage.inst0.ex.eret
// }
io.csr.in.inst(0).pc := io.writeBackStage.inst0.pc
io.csr.in.inst(0).ex := io.writeBackStage.inst0.ex
io.csr.in.inst(1).pc := io.writeBackStage.inst1.pc
io.csr.in.inst(1).ex := io.writeBackStage.inst1.ex
io.fetchUnit.flush := Mux(
io.csr.out.flush,
io.csr.out.flush,
io.writeBackStage.inst0.inst_info.op === EXE_MTC0 && io.ctrl.allow_to_go
)
io.fetchUnit.flush_pc := Mux(io.csr.out.flush, io.csr.out.flush_pc, io.writeBackStage.inst0.pc + 4.U)
io.ctrl.flush_req := io.fetchUnit.flush
io.ctrl.eret := io.writeBackStage.inst0.ex.eret
}