From b75c49177e5a95aca625c7023b3e292e890ddf3c Mon Sep 17 00:00:00 2001 From: Liphen Date: Tue, 21 Nov 2023 15:10:58 +0800 Subject: [PATCH] =?UTF-8?q?=E5=A2=9E=E5=8A=A0=E9=9C=80=E8=A6=81=E5=AE=9E?= =?UTF-8?q?=E7=8E=B0=E7=9A=84csr?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/Core.scala | 2 +- chisel/playground/src/PuaCpu.scala | 2 +- chisel/playground/src/defines/Const.scala | 5 +- .../playground/src/defines/Cp0Bundles.scala | 128 -- .../playground/src/defines/CsrBundles.scala | 90 ++ .../src/defines/isa/Instructions.scala | 1028 ++--------------- .../playground/src/pipeline/execute/Csr.scala | 440 ++----- .../src/pipeline/execute/ExecuteUnit.scala | 6 +- .../src/pipeline/memory/MemoryUnit.scala | 179 ++- 9 files changed, 378 insertions(+), 1502 deletions(-) delete mode 100644 chisel/playground/src/defines/Cp0Bundles.scala create mode 100644 chisel/playground/src/defines/CsrBundles.scala diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala index 13d81d6..d933cdf 100644 --- a/chisel/playground/src/Core.scala +++ b/chisel/playground/src/Core.scala @@ -18,7 +18,7 @@ // class Core(implicit val config: CpuConfig) extends Module { // val io = IO(new Bundle { -// val ext_int = Input(UInt(6.W)) +// val ext_int = Input(UInt(EXT_INT_WID.W)) // val inst = new Cache_ICache() // val data = new Cache_DCache() // val debug = new DEBUG() diff --git a/chisel/playground/src/PuaCpu.scala b/chisel/playground/src/PuaCpu.scala index 108e45e..1d991a4 100644 --- a/chisel/playground/src/PuaCpu.scala +++ b/chisel/playground/src/PuaCpu.scala @@ -7,7 +7,7 @@ // class PuaCpu extends Module { // implicit val config = new CpuConfig() // val io = IO(new Bundle { -// val ext_int = Input(UInt(6.W)) +// val ext_int = Input(UInt(EXT_INT_WID.W)) // val axi = new AXI() // val debug = new DEBUG() // }) diff --git a/chisel/playground/src/defines/Const.scala b/chisel/playground/src/defines/Const.scala index 5fff97a..52a1f42 100644 --- a/chisel/playground/src/defines/Const.scala +++ b/chisel/playground/src/defines/Const.scala @@ -17,8 +17,9 @@ trait Constants extends CoreParameter { val SINGLE_ISSUE = false.B val DUAL_ISSUE = true.B - val INT_WID = 12 - val EXCODE_WID = 16 + val EXT_INT_WID = 3 + val INT_WID = 12 + val EXCODE_WID = 16 // div val DIV_CTRL_WID = 2 diff --git a/chisel/playground/src/defines/Cp0Bundles.scala b/chisel/playground/src/defines/Cp0Bundles.scala deleted file mode 100644 index 4eb55c9..0000000 --- a/chisel/playground/src/defines/Cp0Bundles.scala +++ /dev/null @@ -1,128 +0,0 @@ -// package cpu.defines - -// import chisel3._ -// import chisel3.util._ -// import cpu.defines.Const._ - -// class CsrIndex extends Bundle { -// val p = Bool() -// val blank = UInt((32 - 1 - log2Ceil(TLB_NUM)).W) -// val index = UInt(log2Ceil(TLB_NUM).W) -// } - -// class CsrRandom extends Bundle { -// val blank = UInt((32 - log2Ceil(TLB_NUM)).W) -// val random = UInt(log2Ceil(TLB_NUM).W) -// } - -// class CsrEntryLo extends Bundle { -// val fill = UInt((32 - PFN_WID - C_WID - 3).W) -// val pfn = UInt(PFN_WID.W) -// val c = UInt(C_WID.W) -// val d = Bool() -// val v = Bool() -// val g = Bool() -// } - -// class CsrContext extends Bundle { -// val ptebase = UInt(PTEBASE_WID.W) -// val badvpn2 = UInt(VPN2_WID.W) -// val blank = UInt((32 - PTEBASE_WID - VPN2_WID).W) -// } - -// class CsrWired extends Bundle { -// val blank = UInt((31 - log2Ceil(TLB_NUM)).W) -// val wired = UInt(log2Ceil(TLB_NUM).W) -// } - -// class CsrBadVAddr extends Bundle { -// val badvaddr = UInt(PC_WID.W) -// } - -// class CsrCount extends Bundle { -// val count = UInt(DATA_WID.W) -// } - -// class CsrEntryHi extends Bundle { -// val vpn2 = UInt(VPN2_WID.W) -// val blank = UInt((32 - VPN2_WID - ASID_WID).W) -// val asid = UInt(ASID_WID.W) -// } - -// class CsrCompare extends Bundle { -// val compare = UInt(DATA_WID.W) -// } - -// class CsrStatus extends Bundle { -// val blank3 = UInt(3.W) -// val cu0 = Bool() -// val blank2 = UInt(5.W) -// val bev = Bool() -// val blank1 = UInt(6.W) -// val im = UInt(8.W) -// val blank0 = UInt(3.W) -// val um = Bool() -// val r0 = Bool() -// val erl = Bool() -// val exl = Bool() -// val ie = Bool() -// } - -// class CsrCause extends Bundle { -// val bd = Bool() -// val blank3 = UInt(7.W) -// val iv = Bool() -// val blank2 = UInt(7.W) -// val ip = UInt(8.W) -// val blank1 = Bool() -// val excode = UInt(5.W) -// val blank0 = UInt(2.W) -// } - -// class CsrEpc extends Bundle { -// val epc = UInt(PC_WID.W) -// } - -// class CsrEbase extends Bundle { -// val fill = Bool() -// val blank1 = Bool() -// val ebase = UInt(18.W) -// val blank0 = UInt(2.W) -// val cpuNum = UInt(10.W) -// } - -// class CsrConfig extends Bundle { -// val m = Bool() -// val k23 = UInt(3.W) -// val ku = UInt(3.W) -// val impl = UInt(9.W) -// val be = Bool() -// val at = UInt(2.W) -// val ar = UInt(3.W) -// val mt = UInt(3.W) -// val blank = UInt(3.W) -// val vi = Bool() -// val k0 = UInt(3.W) -// } - -// class CsrConfig1 extends Bundle { -// val m = Bool() -// val ms = UInt(6.W) -// val is = UInt(3.W) -// val il = UInt(3.W) -// val ia = UInt(3.W) -// val ds = UInt(3.W) -// val dl = UInt(3.W) -// val da = UInt(3.W) -// val c2 = Bool() -// val md = Bool() -// val pc = Bool() -// val wr = Bool() -// val ca = Bool() -// val ep = Bool() -// val fp = Bool() -// } - -// class CsrErrorEpc extends Bundle { -// val errorEpc = UInt(PC_WID.W) -// } diff --git a/chisel/playground/src/defines/CsrBundles.scala b/chisel/playground/src/defines/CsrBundles.scala new file mode 100644 index 0000000..ea52f9c --- /dev/null +++ b/chisel/playground/src/defines/CsrBundles.scala @@ -0,0 +1,90 @@ +package cpu.defines + +import chisel3._ +import chisel3.util._ +import cpu.defines.Const._ + +class Mstatus extends Bundle { + val sd = Bool() + val wpri0 = UInt(25.W) + val mbe = Bool() + val sbe = Bool() + val sxl = UInt(2.W) + val uxl = UInt(2.W) + val wpri1 = UInt(9.W) + val tsr = Bool() + val tw = Bool() + val tvm = Bool() + val mxr = Bool() + val sum = Bool() + val mprv = Bool() + val xs = UInt(2.W) + val fs = UInt(2.W) + val mpp = UInt(2.W) + val vs = UInt(2.W) + val spp = Bool() + val mpie = Bool() + val ube = Bool() + val spie = Bool() + val wpri2 = Bool() + val mie = Bool() + val wpri3 = Bool() + val sie = Bool() + val wpri4 = Bool() +} + +class Misa extends Bundle { + val mxl = UInt(2.W) + val blank = UInt((XLEN - 28).W) + val extensions = UInt(26.W) +} + +class Mtvec extends Bundle { + val base = UInt((XLEN - 2).W) + val mode = UInt(2.W) +} + +class Mcause extends Bundle { + val interrupt = Bool() + val excode = UInt((XLEN - 1).W) +} + +class Mip extends Bundle { + val blank0 = UInt(52.W) + val meip = Bool() + val blank1 = UInt(2.W) + val seip = Bool() + val blank2 = UInt(2.W) + val mtip = Bool() + val blank3 = UInt(2.W) + val stip = Bool() + val blank4 = UInt(2.W) + val msip = Bool() + val blank5 = UInt(2.W) + val ssip = Bool() + val blank6 = UInt(2.W) +} + +class Mie extends Bundle { + val blank0 = UInt(52.W) + val meie = Bool() + val blank1 = UInt(2.W) + val seie = Bool() + val blank2 = UInt(2.W) + val mtie = Bool() + val blank3 = UInt(2.W) + val stie = Bool() + val blank4 = UInt(2.W) + val msie = Bool() + val blank5 = UInt(2.W) + val ssie = Bool() + val blank6 = UInt(2.W) +} + +object Priv { + def u = "b00".U + def s = "b01".U + def h = "b10".U + def m = "b11".U + def apply() = UInt(2.W) +} diff --git a/chisel/playground/src/defines/isa/Instructions.scala b/chisel/playground/src/defines/isa/Instructions.scala index 1197822..36380ff 100644 --- a/chisel/playground/src/defines/isa/Instructions.scala +++ b/chisel/playground/src/defines/isa/Instructions.scala @@ -173,6 +173,121 @@ object CSROpType { def clri = "b111".U } +trait HasCSRConst { + // User Trap Setup + val Ustatus = 0x000 + val Uie = 0x004 + val Utvec = 0x005 + + // User Trap Handling + val Uscratch = 0x040 + val Uepc = 0x041 + val Ucause = 0x042 + val Utval = 0x043 + val Uip = 0x044 + + // User Floating-Point CSRs (not implemented) + val Fflags = 0x001 + val Frm = 0x002 + val Fcsr = 0x003 + + // User Counter/Timers + val Cycle = 0xc00 + val Time = 0xc01 + val Instret = 0xc02 + + // Supervisor Trap Setup + val Sstatus = 0x100 + val Sedeleg = 0x102 + val Sideleg = 0x103 + val Sie = 0x104 + val Stvec = 0x105 + val Scounteren = 0x106 + + // Supervisor Trap Handling + val Sscratch = 0x140 + val Sepc = 0x141 + val Scause = 0x142 + val Stval = 0x143 + val Sip = 0x144 + + // Supervisor Protection and Translation + val Satp = 0x180 + + // Machine Information Registers + val Mvendorid = 0xf11 + val Marchid = 0xf12 + val Mimpid = 0xf13 + val Mhartid = 0xf14 + + // Machine Trap Setup + val Mstatus = 0x300 + val Misa = 0x301 + val Medeleg = 0x302 + val Mideleg = 0x303 + val Mie = 0x304 + val Mtvec = 0x305 + val Mcounteren = 0x306 + + // Machine Trap Handling + val Mscratch = 0x340 + val Mepc = 0x341 + val Mcause = 0x342 + val Mtval = 0x343 + val Mip = 0x344 + + // Machine Memory Protection + // TBD + val Pmpcfg0 = 0x3a0 + val Pmpcfg1 = 0x3a1 + val Pmpcfg2 = 0x3a2 + val Pmpcfg3 = 0x3a3 + val PmpaddrBase = 0x3b0 + + // Machine Counter/Timers + // Currently, NutCore uses perfcnt csr set instead of standard Machine Counter/Timers + // 0xB80 - 0x89F are also used as perfcnt csr + + // Machine Counter Setup (not implemented) + // Debug/Trace Registers (shared with Debug Mode) (not implemented) + // Debug Mode Registers (not implemented) + + def privEcall = 0x000.U + def privEbreak = 0x001.U + def privMret = 0x302.U + def privSret = 0x102.U + def privUret = 0x002.U + + def ModeM = 0x3.U + def ModeH = 0x2.U + def ModeS = 0x1.U + def ModeU = 0x0.U + + def IRQ_UEIP = 0 + def IRQ_SEIP = 1 + def IRQ_MEIP = 3 + + def IRQ_UTIP = 4 + def IRQ_STIP = 5 + def IRQ_MTIP = 7 + + def IRQ_USIP = 8 + def IRQ_SSIP = 9 + def IRQ_MSIP = 11 + + val IntPriority = Seq( + IRQ_MEIP, + IRQ_MSIP, + IRQ_MTIP, + IRQ_SEIP, + IRQ_SSIP, + IRQ_STIP, + IRQ_UEIP, + IRQ_USIP, + IRQ_UTIP + ) +} + trait HasExceptionNO { def instrAddrMisaligned = 0 def instrAccessFault = 1 @@ -206,916 +321,3 @@ trait HasExceptionNO { loadAccessFault ) } - -object Causes { - val misaligned_fetch = 0x0 - val fetch_access = 0x1 - val illegal_instruction = 0x2 - val breakpoint = 0x3 - val misaligned_load = 0x4 - val load_access = 0x5 - val misaligned_store = 0x6 - val store_access = 0x7 - val user_ecall = 0x8 - val supervisor_ecall = 0x9 - val virtual_supervisor_ecall = 0xa - val machine_ecall = 0xb - val fetch_page_fault = 0xc - val load_page_fault = 0xd - val store_page_fault = 0xf - val fetch_guest_page_fault = 0x14 - val load_guest_page_fault = 0x15 - val virtual_instruction = 0x16 - val store_guest_page_fault = 0x17 - val all = { - val res = collection.mutable.ArrayBuffer[Int]() - res += misaligned_fetch - res += fetch_access - res += illegal_instruction - res += breakpoint - res += misaligned_load - res += load_access - res += misaligned_store - res += store_access - res += user_ecall - res += supervisor_ecall - res += virtual_supervisor_ecall - res += machine_ecall - res += fetch_page_fault - res += load_page_fault - res += store_page_fault - res += fetch_guest_page_fault - res += load_guest_page_fault - res += virtual_instruction - res += store_guest_page_fault - res.toArray - } -} -object CSRs { - val fflags = 0x1 - val frm = 0x2 - val fcsr = 0x3 - val vstart = 0x8 - val vxsat = 0x9 - val vxrm = 0xa - val vcsr = 0xf - val seed = 0x15 - val jvt = 0x17 - val cycle = 0xc00 - val time = 0xc01 - val instret = 0xc02 - val hpmcounter3 = 0xc03 - val hpmcounter4 = 0xc04 - val hpmcounter5 = 0xc05 - val hpmcounter6 = 0xc06 - val hpmcounter7 = 0xc07 - val hpmcounter8 = 0xc08 - val hpmcounter9 = 0xc09 - val hpmcounter10 = 0xc0a - val hpmcounter11 = 0xc0b - val hpmcounter12 = 0xc0c - val hpmcounter13 = 0xc0d - val hpmcounter14 = 0xc0e - val hpmcounter15 = 0xc0f - val hpmcounter16 = 0xc10 - val hpmcounter17 = 0xc11 - val hpmcounter18 = 0xc12 - val hpmcounter19 = 0xc13 - val hpmcounter20 = 0xc14 - val hpmcounter21 = 0xc15 - val hpmcounter22 = 0xc16 - val hpmcounter23 = 0xc17 - val hpmcounter24 = 0xc18 - val hpmcounter25 = 0xc19 - val hpmcounter26 = 0xc1a - val hpmcounter27 = 0xc1b - val hpmcounter28 = 0xc1c - val hpmcounter29 = 0xc1d - val hpmcounter30 = 0xc1e - val hpmcounter31 = 0xc1f - val vl = 0xc20 - val vtype = 0xc21 - val vlenb = 0xc22 - val sstatus = 0x100 - val sedeleg = 0x102 - val sideleg = 0x103 - val sie = 0x104 - val stvec = 0x105 - val scounteren = 0x106 - val senvcfg = 0x10a - val sstateen0 = 0x10c - val sstateen1 = 0x10d - val sstateen2 = 0x10e - val sstateen3 = 0x10f - val sscratch = 0x140 - val sepc = 0x141 - val scause = 0x142 - val stval = 0x143 - val sip = 0x144 - val stimecmp = 0x14d - val siselect = 0x150 - val sireg = 0x151 - val stopei = 0x15c - val satp = 0x180 - val scontext = 0x5a8 - val vsstatus = 0x200 - val vsie = 0x204 - val vstvec = 0x205 - val vsscratch = 0x240 - val vsepc = 0x241 - val vscause = 0x242 - val vstval = 0x243 - val vsip = 0x244 - val vstimecmp = 0x24d - val vsiselect = 0x250 - val vsireg = 0x251 - val vstopei = 0x25c - val vsatp = 0x280 - val hstatus = 0x600 - val hedeleg = 0x602 - val hideleg = 0x603 - val hie = 0x604 - val htimedelta = 0x605 - val hcounteren = 0x606 - val hgeie = 0x607 - val hvien = 0x608 - val hvictl = 0x609 - val henvcfg = 0x60a - val hstateen0 = 0x60c - val hstateen1 = 0x60d - val hstateen2 = 0x60e - val hstateen3 = 0x60f - val htval = 0x643 - val hip = 0x644 - val hvip = 0x645 - val hviprio1 = 0x646 - val hviprio2 = 0x647 - val htinst = 0x64a - val hgatp = 0x680 - val hcontext = 0x6a8 - val hgeip = 0xe12 - val vstopi = 0xeb0 - val scountovf = 0xda0 - val stopi = 0xdb0 - val utvt = 0x7 - val unxti = 0x45 - val uintstatus = 0x46 - val uscratchcsw = 0x48 - val uscratchcswl = 0x49 - val stvt = 0x107 - val snxti = 0x145 - val sintstatus = 0x146 - val sscratchcsw = 0x148 - val sscratchcswl = 0x149 - val mtvt = 0x307 - val mnxti = 0x345 - val mintstatus = 0x346 - val mscratchcsw = 0x348 - val mscratchcswl = 0x349 - val mstatus = 0x300 - val misa = 0x301 - val medeleg = 0x302 - val mideleg = 0x303 - val mie = 0x304 - val mtvec = 0x305 - val mcounteren = 0x306 - val mvien = 0x308 - val mvip = 0x309 - val menvcfg = 0x30a - val mstateen0 = 0x30c - val mstateen1 = 0x30d - val mstateen2 = 0x30e - val mstateen3 = 0x30f - val mcountinhibit = 0x320 - val mscratch = 0x340 - val mepc = 0x341 - val mcause = 0x342 - val mtval = 0x343 - val mip = 0x344 - val mtinst = 0x34a - val mtval2 = 0x34b - val miselect = 0x350 - val mireg = 0x351 - val mtopei = 0x35c - val pmpcfg0 = 0x3a0 - val pmpcfg1 = 0x3a1 - val pmpcfg2 = 0x3a2 - val pmpcfg3 = 0x3a3 - val pmpcfg4 = 0x3a4 - val pmpcfg5 = 0x3a5 - val pmpcfg6 = 0x3a6 - val pmpcfg7 = 0x3a7 - val pmpcfg8 = 0x3a8 - val pmpcfg9 = 0x3a9 - val pmpcfg10 = 0x3aa - val pmpcfg11 = 0x3ab - val pmpcfg12 = 0x3ac - val pmpcfg13 = 0x3ad - val pmpcfg14 = 0x3ae - val pmpcfg15 = 0x3af - val pmpaddr0 = 0x3b0 - val pmpaddr1 = 0x3b1 - val pmpaddr2 = 0x3b2 - val pmpaddr3 = 0x3b3 - val pmpaddr4 = 0x3b4 - val pmpaddr5 = 0x3b5 - val pmpaddr6 = 0x3b6 - val pmpaddr7 = 0x3b7 - val pmpaddr8 = 0x3b8 - val pmpaddr9 = 0x3b9 - val pmpaddr10 = 0x3ba - val pmpaddr11 = 0x3bb - val pmpaddr12 = 0x3bc - val pmpaddr13 = 0x3bd - val pmpaddr14 = 0x3be - val pmpaddr15 = 0x3bf - val pmpaddr16 = 0x3c0 - val pmpaddr17 = 0x3c1 - val pmpaddr18 = 0x3c2 - val pmpaddr19 = 0x3c3 - val pmpaddr20 = 0x3c4 - val pmpaddr21 = 0x3c5 - val pmpaddr22 = 0x3c6 - val pmpaddr23 = 0x3c7 - val pmpaddr24 = 0x3c8 - val pmpaddr25 = 0x3c9 - val pmpaddr26 = 0x3ca - val pmpaddr27 = 0x3cb - val pmpaddr28 = 0x3cc - val pmpaddr29 = 0x3cd - val pmpaddr30 = 0x3ce - val pmpaddr31 = 0x3cf - val pmpaddr32 = 0x3d0 - val pmpaddr33 = 0x3d1 - val pmpaddr34 = 0x3d2 - val pmpaddr35 = 0x3d3 - val pmpaddr36 = 0x3d4 - val pmpaddr37 = 0x3d5 - val pmpaddr38 = 0x3d6 - val pmpaddr39 = 0x3d7 - val pmpaddr40 = 0x3d8 - val pmpaddr41 = 0x3d9 - val pmpaddr42 = 0x3da - val pmpaddr43 = 0x3db - val pmpaddr44 = 0x3dc - val pmpaddr45 = 0x3dd - val pmpaddr46 = 0x3de - val pmpaddr47 = 0x3df - val pmpaddr48 = 0x3e0 - val pmpaddr49 = 0x3e1 - val pmpaddr50 = 0x3e2 - val pmpaddr51 = 0x3e3 - val pmpaddr52 = 0x3e4 - val pmpaddr53 = 0x3e5 - val pmpaddr54 = 0x3e6 - val pmpaddr55 = 0x3e7 - val pmpaddr56 = 0x3e8 - val pmpaddr57 = 0x3e9 - val pmpaddr58 = 0x3ea - val pmpaddr59 = 0x3eb - val pmpaddr60 = 0x3ec - val pmpaddr61 = 0x3ed - val pmpaddr62 = 0x3ee - val pmpaddr63 = 0x3ef - val mseccfg = 0x747 - val tselect = 0x7a0 - val tdata1 = 0x7a1 - val tdata2 = 0x7a2 - val tdata3 = 0x7a3 - val tinfo = 0x7a4 - val tcontrol = 0x7a5 - val mcontext = 0x7a8 - val mscontext = 0x7aa - val dcsr = 0x7b0 - val dpc = 0x7b1 - val dscratch0 = 0x7b2 - val dscratch1 = 0x7b3 - val mcycle = 0xb00 - val minstret = 0xb02 - val mhpmcounter3 = 0xb03 - val mhpmcounter4 = 0xb04 - val mhpmcounter5 = 0xb05 - val mhpmcounter6 = 0xb06 - val mhpmcounter7 = 0xb07 - val mhpmcounter8 = 0xb08 - val mhpmcounter9 = 0xb09 - val mhpmcounter10 = 0xb0a - val mhpmcounter11 = 0xb0b - val mhpmcounter12 = 0xb0c - val mhpmcounter13 = 0xb0d - val mhpmcounter14 = 0xb0e - val mhpmcounter15 = 0xb0f - val mhpmcounter16 = 0xb10 - val mhpmcounter17 = 0xb11 - val mhpmcounter18 = 0xb12 - val mhpmcounter19 = 0xb13 - val mhpmcounter20 = 0xb14 - val mhpmcounter21 = 0xb15 - val mhpmcounter22 = 0xb16 - val mhpmcounter23 = 0xb17 - val mhpmcounter24 = 0xb18 - val mhpmcounter25 = 0xb19 - val mhpmcounter26 = 0xb1a - val mhpmcounter27 = 0xb1b - val mhpmcounter28 = 0xb1c - val mhpmcounter29 = 0xb1d - val mhpmcounter30 = 0xb1e - val mhpmcounter31 = 0xb1f - val mhpmevent3 = 0x323 - val mhpmevent4 = 0x324 - val mhpmevent5 = 0x325 - val mhpmevent6 = 0x326 - val mhpmevent7 = 0x327 - val mhpmevent8 = 0x328 - val mhpmevent9 = 0x329 - val mhpmevent10 = 0x32a - val mhpmevent11 = 0x32b - val mhpmevent12 = 0x32c - val mhpmevent13 = 0x32d - val mhpmevent14 = 0x32e - val mhpmevent15 = 0x32f - val mhpmevent16 = 0x330 - val mhpmevent17 = 0x331 - val mhpmevent18 = 0x332 - val mhpmevent19 = 0x333 - val mhpmevent20 = 0x334 - val mhpmevent21 = 0x335 - val mhpmevent22 = 0x336 - val mhpmevent23 = 0x337 - val mhpmevent24 = 0x338 - val mhpmevent25 = 0x339 - val mhpmevent26 = 0x33a - val mhpmevent27 = 0x33b - val mhpmevent28 = 0x33c - val mhpmevent29 = 0x33d - val mhpmevent30 = 0x33e - val mhpmevent31 = 0x33f - val mvendorid = 0xf11 - val marchid = 0xf12 - val mimpid = 0xf13 - val mhartid = 0xf14 - val mconfigptr = 0xf15 - val mtopi = 0xfb0 - val sieh = 0x114 - val siph = 0x154 - val stimecmph = 0x15d - val vsieh = 0x214 - val vsiph = 0x254 - val vstimecmph = 0x25d - val htimedeltah = 0x615 - val hidelegh = 0x613 - val hvienh = 0x618 - val henvcfgh = 0x61a - val hviph = 0x655 - val hviprio1h = 0x656 - val hviprio2h = 0x657 - val hstateen0h = 0x61c - val hstateen1h = 0x61d - val hstateen2h = 0x61e - val hstateen3h = 0x61f - val cycleh = 0xc80 - val timeh = 0xc81 - val instreth = 0xc82 - val hpmcounter3h = 0xc83 - val hpmcounter4h = 0xc84 - val hpmcounter5h = 0xc85 - val hpmcounter6h = 0xc86 - val hpmcounter7h = 0xc87 - val hpmcounter8h = 0xc88 - val hpmcounter9h = 0xc89 - val hpmcounter10h = 0xc8a - val hpmcounter11h = 0xc8b - val hpmcounter12h = 0xc8c - val hpmcounter13h = 0xc8d - val hpmcounter14h = 0xc8e - val hpmcounter15h = 0xc8f - val hpmcounter16h = 0xc90 - val hpmcounter17h = 0xc91 - val hpmcounter18h = 0xc92 - val hpmcounter19h = 0xc93 - val hpmcounter20h = 0xc94 - val hpmcounter21h = 0xc95 - val hpmcounter22h = 0xc96 - val hpmcounter23h = 0xc97 - val hpmcounter24h = 0xc98 - val hpmcounter25h = 0xc99 - val hpmcounter26h = 0xc9a - val hpmcounter27h = 0xc9b - val hpmcounter28h = 0xc9c - val hpmcounter29h = 0xc9d - val hpmcounter30h = 0xc9e - val hpmcounter31h = 0xc9f - val mstatush = 0x310 - val midelegh = 0x313 - val mieh = 0x314 - val mvienh = 0x318 - val mviph = 0x319 - val menvcfgh = 0x31a - val mstateen0h = 0x31c - val mstateen1h = 0x31d - val mstateen2h = 0x31e - val mstateen3h = 0x31f - val miph = 0x354 - val mhpmevent3h = 0x723 - val mhpmevent4h = 0x724 - val mhpmevent5h = 0x725 - val mhpmevent6h = 0x726 - val mhpmevent7h = 0x727 - val mhpmevent8h = 0x728 - val mhpmevent9h = 0x729 - val mhpmevent10h = 0x72a - val mhpmevent11h = 0x72b - val mhpmevent12h = 0x72c - val mhpmevent13h = 0x72d - val mhpmevent14h = 0x72e - val mhpmevent15h = 0x72f - val mhpmevent16h = 0x730 - val mhpmevent17h = 0x731 - val mhpmevent18h = 0x732 - val mhpmevent19h = 0x733 - val mhpmevent20h = 0x734 - val mhpmevent21h = 0x735 - val mhpmevent22h = 0x736 - val mhpmevent23h = 0x737 - val mhpmevent24h = 0x738 - val mhpmevent25h = 0x739 - val mhpmevent26h = 0x73a - val mhpmevent27h = 0x73b - val mhpmevent28h = 0x73c - val mhpmevent29h = 0x73d - val mhpmevent30h = 0x73e - val mhpmevent31h = 0x73f - val mnscratch = 0x740 - val mnepc = 0x741 - val mncause = 0x742 - val mnstatus = 0x744 - val mseccfgh = 0x757 - val mcycleh = 0xb80 - val minstreth = 0xb82 - val mhpmcounter3h = 0xb83 - val mhpmcounter4h = 0xb84 - val mhpmcounter5h = 0xb85 - val mhpmcounter6h = 0xb86 - val mhpmcounter7h = 0xb87 - val mhpmcounter8h = 0xb88 - val mhpmcounter9h = 0xb89 - val mhpmcounter10h = 0xb8a - val mhpmcounter11h = 0xb8b - val mhpmcounter12h = 0xb8c - val mhpmcounter13h = 0xb8d - val mhpmcounter14h = 0xb8e - val mhpmcounter15h = 0xb8f - val mhpmcounter16h = 0xb90 - val mhpmcounter17h = 0xb91 - val mhpmcounter18h = 0xb92 - val mhpmcounter19h = 0xb93 - val mhpmcounter20h = 0xb94 - val mhpmcounter21h = 0xb95 - val mhpmcounter22h = 0xb96 - val mhpmcounter23h = 0xb97 - val mhpmcounter24h = 0xb98 - val mhpmcounter25h = 0xb99 - val mhpmcounter26h = 0xb9a - val mhpmcounter27h = 0xb9b - val mhpmcounter28h = 0xb9c - val mhpmcounter29h = 0xb9d - val mhpmcounter30h = 0xb9e - val mhpmcounter31h = 0xb9f - val all = { - val res = collection.mutable.ArrayBuffer[Int]() - res += fflags - res += frm - res += fcsr - res += vstart - res += vxsat - res += vxrm - res += vcsr - res += seed - res += jvt - res += cycle - res += time - res += instret - res += hpmcounter3 - res += hpmcounter4 - res += hpmcounter5 - res += hpmcounter6 - res += hpmcounter7 - res += hpmcounter8 - res += hpmcounter9 - res += hpmcounter10 - res += hpmcounter11 - res += hpmcounter12 - res += hpmcounter13 - res += hpmcounter14 - res += hpmcounter15 - res += hpmcounter16 - res += hpmcounter17 - res += hpmcounter18 - res += hpmcounter19 - res += hpmcounter20 - res += hpmcounter21 - res += hpmcounter22 - res += hpmcounter23 - res += hpmcounter24 - res += hpmcounter25 - res += hpmcounter26 - res += hpmcounter27 - res += hpmcounter28 - res += hpmcounter29 - res += hpmcounter30 - res += hpmcounter31 - res += vl - res += vtype - res += vlenb - res += sstatus - res += sedeleg - res += sideleg - res += sie - res += stvec - res += scounteren - res += senvcfg - res += sstateen0 - res += sstateen1 - res += sstateen2 - res += sstateen3 - res += sscratch - res += sepc - res += scause - res += stval - res += sip - res += stimecmp - res += siselect - res += sireg - res += stopei - res += satp - res += scontext - res += vsstatus - res += vsie - res += vstvec - res += vsscratch - res += vsepc - res += vscause - res += vstval - res += vsip - res += vstimecmp - res += vsiselect - res += vsireg - res += vstopei - res += vsatp - res += hstatus - res += hedeleg - res += hideleg - res += hie - res += htimedelta - res += hcounteren - res += hgeie - res += hvien - res += hvictl - res += henvcfg - res += hstateen0 - res += hstateen1 - res += hstateen2 - res += hstateen3 - res += htval - res += hip - res += hvip - res += hviprio1 - res += hviprio2 - res += htinst - res += hgatp - res += hcontext - res += hgeip - res += vstopi - res += scountovf - res += stopi - res += utvt - res += unxti - res += uintstatus - res += uscratchcsw - res += uscratchcswl - res += stvt - res += snxti - res += sintstatus - res += sscratchcsw - res += sscratchcswl - res += mtvt - res += mnxti - res += mintstatus - res += mscratchcsw - res += mscratchcswl - res += mstatus - res += misa - res += medeleg - res += mideleg - res += mie - res += mtvec - res += mcounteren - res += mvien - res += mvip - res += menvcfg - res += mstateen0 - res += mstateen1 - res += mstateen2 - res += mstateen3 - res += mcountinhibit - res += mscratch - res += mepc - res += mcause - res += mtval - res += mip - res += mtinst - res += mtval2 - res += miselect - res += mireg - res += mtopei - res += pmpcfg0 - res += pmpcfg1 - res += pmpcfg2 - res += pmpcfg3 - res += pmpcfg4 - res += pmpcfg5 - res += pmpcfg6 - res += pmpcfg7 - res += pmpcfg8 - res += pmpcfg9 - res += pmpcfg10 - res += pmpcfg11 - res += pmpcfg12 - res += pmpcfg13 - res += pmpcfg14 - res += pmpcfg15 - res += pmpaddr0 - res += pmpaddr1 - res += pmpaddr2 - res += pmpaddr3 - res += pmpaddr4 - res += pmpaddr5 - res += pmpaddr6 - res += pmpaddr7 - res += pmpaddr8 - res += pmpaddr9 - res += pmpaddr10 - res += pmpaddr11 - res += pmpaddr12 - res += pmpaddr13 - res += pmpaddr14 - res += pmpaddr15 - res += pmpaddr16 - res += pmpaddr17 - res += pmpaddr18 - res += pmpaddr19 - res += pmpaddr20 - res += pmpaddr21 - res += pmpaddr22 - res += pmpaddr23 - res += pmpaddr24 - res += pmpaddr25 - res += pmpaddr26 - res += pmpaddr27 - res += pmpaddr28 - res += pmpaddr29 - res += pmpaddr30 - res += pmpaddr31 - res += pmpaddr32 - res += pmpaddr33 - res += pmpaddr34 - res += pmpaddr35 - res += pmpaddr36 - res += pmpaddr37 - res += pmpaddr38 - res += pmpaddr39 - res += pmpaddr40 - res += pmpaddr41 - res += pmpaddr42 - res += pmpaddr43 - res += pmpaddr44 - res += pmpaddr45 - res += pmpaddr46 - res += pmpaddr47 - res += pmpaddr48 - res += pmpaddr49 - res += pmpaddr50 - res += pmpaddr51 - res += pmpaddr52 - res += pmpaddr53 - res += pmpaddr54 - res += pmpaddr55 - res += pmpaddr56 - res += pmpaddr57 - res += pmpaddr58 - res += pmpaddr59 - res += pmpaddr60 - res += pmpaddr61 - res += pmpaddr62 - res += pmpaddr63 - res += mseccfg - res += tselect - res += tdata1 - res += tdata2 - res += tdata3 - res += tinfo - res += tcontrol - res += mcontext - res += mscontext - res += dcsr - res += dpc - res += dscratch0 - res += dscratch1 - res += mcycle - res += minstret - res += mhpmcounter3 - res += mhpmcounter4 - res += mhpmcounter5 - res += mhpmcounter6 - res += mhpmcounter7 - res += mhpmcounter8 - res += mhpmcounter9 - res += mhpmcounter10 - res += mhpmcounter11 - res += mhpmcounter12 - res += mhpmcounter13 - res += mhpmcounter14 - res += mhpmcounter15 - res += mhpmcounter16 - res += mhpmcounter17 - res += mhpmcounter18 - res += mhpmcounter19 - res += mhpmcounter20 - res += mhpmcounter21 - res += mhpmcounter22 - res += mhpmcounter23 - res += mhpmcounter24 - res += mhpmcounter25 - res += mhpmcounter26 - res += mhpmcounter27 - res += mhpmcounter28 - res += mhpmcounter29 - res += mhpmcounter30 - res += mhpmcounter31 - res += mhpmevent3 - res += mhpmevent4 - res += mhpmevent5 - res += mhpmevent6 - res += mhpmevent7 - res += mhpmevent8 - res += mhpmevent9 - res += mhpmevent10 - res += mhpmevent11 - res += mhpmevent12 - res += mhpmevent13 - res += mhpmevent14 - res += mhpmevent15 - res += mhpmevent16 - res += mhpmevent17 - res += mhpmevent18 - res += mhpmevent19 - res += mhpmevent20 - res += mhpmevent21 - res += mhpmevent22 - res += mhpmevent23 - res += mhpmevent24 - res += mhpmevent25 - res += mhpmevent26 - res += mhpmevent27 - res += mhpmevent28 - res += mhpmevent29 - res += mhpmevent30 - res += mhpmevent31 - res += mvendorid - res += marchid - res += mimpid - res += mhartid - res += mconfigptr - res += mtopi - res.toArray - } - val all32 = { - val res = collection.mutable.ArrayBuffer(all: _*) - res += sieh - res += siph - res += stimecmph - res += vsieh - res += vsiph - res += vstimecmph - res += htimedeltah - res += hidelegh - res += hvienh - res += henvcfgh - res += hviph - res += hviprio1h - res += hviprio2h - res += hstateen0h - res += hstateen1h - res += hstateen2h - res += hstateen3h - res += cycleh - res += timeh - res += instreth - res += hpmcounter3h - res += hpmcounter4h - res += hpmcounter5h - res += hpmcounter6h - res += hpmcounter7h - res += hpmcounter8h - res += hpmcounter9h - res += hpmcounter10h - res += hpmcounter11h - res += hpmcounter12h - res += hpmcounter13h - res += hpmcounter14h - res += hpmcounter15h - res += hpmcounter16h - res += hpmcounter17h - res += hpmcounter18h - res += hpmcounter19h - res += hpmcounter20h - res += hpmcounter21h - res += hpmcounter22h - res += hpmcounter23h - res += hpmcounter24h - res += hpmcounter25h - res += hpmcounter26h - res += hpmcounter27h - res += hpmcounter28h - res += hpmcounter29h - res += hpmcounter30h - res += hpmcounter31h - res += mstatush - res += midelegh - res += mieh - res += mvienh - res += mviph - res += menvcfgh - res += mstateen0h - res += mstateen1h - res += mstateen2h - res += mstateen3h - res += miph - res += mhpmevent3h - res += mhpmevent4h - res += mhpmevent5h - res += mhpmevent6h - res += mhpmevent7h - res += mhpmevent8h - res += mhpmevent9h - res += mhpmevent10h - res += mhpmevent11h - res += mhpmevent12h - res += mhpmevent13h - res += mhpmevent14h - res += mhpmevent15h - res += mhpmevent16h - res += mhpmevent17h - res += mhpmevent18h - res += mhpmevent19h - res += mhpmevent20h - res += mhpmevent21h - res += mhpmevent22h - res += mhpmevent23h - res += mhpmevent24h - res += mhpmevent25h - res += mhpmevent26h - res += mhpmevent27h - res += mhpmevent28h - res += mhpmevent29h - res += mhpmevent30h - res += mhpmevent31h - res += mnscratch - res += mnepc - res += mncause - res += mnstatus - res += mseccfgh - res += mcycleh - res += minstreth - res += mhpmcounter3h - res += mhpmcounter4h - res += mhpmcounter5h - res += mhpmcounter6h - res += mhpmcounter7h - res += mhpmcounter8h - res += mhpmcounter9h - res += mhpmcounter10h - res += mhpmcounter11h - res += mhpmcounter12h - res += mhpmcounter13h - res += mhpmcounter14h - res += mhpmcounter15h - res += mhpmcounter16h - res += mhpmcounter17h - res += mhpmcounter18h - res += mhpmcounter19h - res += mhpmcounter20h - res += mhpmcounter21h - res += mhpmcounter22h - res += mhpmcounter23h - res += mhpmcounter24h - res += mhpmcounter25h - res += mhpmcounter26h - res += mhpmcounter27h - res += mhpmcounter28h - res += mhpmcounter29h - res += mhpmcounter30h - res += mhpmcounter31h - res.toArray - } -} diff --git a/chisel/playground/src/pipeline/execute/Csr.scala b/chisel/playground/src/pipeline/execute/Csr.scala index 1dbc355..437690d 100644 --- a/chisel/playground/src/pipeline/execute/Csr.scala +++ b/chisel/playground/src/pipeline/execute/Csr.scala @@ -1,368 +1,88 @@ -// package cpu.pipeline.execute +package cpu.pipeline.execute -// import chisel3._ -// import chisel3.util._ -// import cpu.defines._ -// import cpu.defines.Const._ -// import cpu.pipeline.memory.CsrInfo -// import cpu.CpuConfig -// import cpu.pipeline.decoder.CsrDecoderUnit +import chisel3._ +import chisel3.util._ +import cpu.defines._ +import cpu.defines.Const._ +import cpu.pipeline.memory.CsrInfo +import cpu.CpuConfig +import cpu.pipeline.decoder.CsrDecoderUnit -// class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle { -// val in = Input(new Bundle { -// val inst = Vec( -// config.fuNum, -// new Bundle { -// val pc = UInt(PC_WID.W) -// val ex = new ExceptionInfo() -// } -// ) -// }) -// val out = Output(new Bundle { -// val flush = Bool() -// val flush_pc = UInt(PC_WID.W) -// }) -// } +class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle { + val in = Input(new Bundle { + val inst = Vec( + config.fuNum, + new Bundle { + val pc = UInt(PC_WID.W) + val ex = new ExceptionInfo() + } + ) + }) + val out = Output(new Bundle { + val flush = Bool() + val flush_pc = UInt(PC_WID.W) + }) +} -// class CsrExecuteUnit(implicit val config: CpuConfig) extends Bundle { -// val in = Input(new Bundle { -// val inst_info = Vec(config.fuNum, new InstInfo()) -// val mtc0_wdata = UInt(DATA_WID.W) -// }) -// val out = Output(new Bundle { -// val csr_rdata = Vec(config.fuNum, UInt(DATA_WID.W)) -// val debug = Output(new CsrInfo()) -// }) -// } +class CsrExecuteUnit(implicit val config: CpuConfig) extends Bundle { + val in = Input(new Bundle { + val inst_info = Vec(config.fuNum, new InstInfo()) + val mtc0_wdata = UInt(DATA_WID.W) + }) + val out = Output(new Bundle { + val csr_rdata = Vec(config.fuNum, UInt(DATA_WID.W)) + val debug = Output(new CsrInfo()) + }) +} -// class Csr(implicit val config: CpuConfig) extends Module { -// val io = IO(new Bundle { -// val ext_int = Input(UInt(EXT_INT_WID.W)) -// val ctrl = Input(new Bundle { -// val exe_stall = Bool() -// val mem_stall = Bool() -// }) -// val decoderUnit = Output(new CsrDecoderUnit()) -// val executeUnit = new CsrExecuteUnit() -// val memoryUnit = new CsrMemoryUnit() -// }) -// // 优先使用inst0的信息 -// val ex_sel = io.memoryUnit.in.inst(0).ex.flush_req || !io.memoryUnit.in.inst(1).ex.flush_req -// val pc = Mux(ex_sel, io.memoryUnit.in.inst(0).pc, io.memoryUnit.in.inst(1).pc) -// val ex = Mux(ex_sel, io.memoryUnit.in.inst(0).ex, io.memoryUnit.in.inst(1).ex) -// val mtc0_wen = io.executeUnit.in.inst_info(0).op === EXE_MTC0 -// val mtc0_wdata = io.executeUnit.in.mtc0_wdata -// val mtc0_addr = io.executeUnit.in.inst_info(0).csr_addr -// val exe_op = io.executeUnit.in.inst_info(0).op -// val exe_stall = io.ctrl.exe_stall -// val mem_stall = io.ctrl.mem_stall +class Csr(implicit val config: CpuConfig) extends Module { + val io = IO(new Bundle { + val ext_int = Input(UInt(EXT_INT_WID.W)) + val ctrl = Input(new Bundle { + val exe_stall = Bool() + val mem_stall = Bool() + }) + val decoderUnit = Output(new CsrDecoderUnit()) + val executeUnit = new CsrExecuteUnit() + val memoryUnit = new CsrMemoryUnit() + }) + // 优先使用inst0的信息 + val ex_sel = io.memoryUnit.in.inst(0).ex.flush_req || !io.memoryUnit.in.inst(1).ex.flush_req + val pc = Mux(ex_sel, io.memoryUnit.in.inst(0).pc, io.memoryUnit.in.inst(1).pc) + val ex = Mux(ex_sel, io.memoryUnit.in.inst(0).ex, io.memoryUnit.in.inst(1).ex) + val exe_op = io.executeUnit.in.inst_info(0).op + val exe_stall = io.ctrl.exe_stall + val mem_stall = io.ctrl.mem_stall -// // ---------------csr-defines----------------- + val cycle = RegInit(0.U(XLEN.W)) // 时钟周期计数器 -// // index register (0,0) -// val csr_index = RegInit(0.U.asTypeOf(new CsrIndex())) + val instret = RegInit(0.U(XLEN.W)) // 指令计数器 -// // random register (1,0) -// val random_init = Wire(new CsrRandom()) -// random_init := 0.U.asTypeOf(new CsrRandom()) -// random_init.random := (TLB_NUM - 1).U -// val csr_random = RegInit(random_init) + val mvendorid = RegInit(0.U(XLEN.W)) // 厂商ID + val marchid = RegInit(0.U(XLEN.W)) // 架构ID + val mimpid = RegInit(0.U(XLEN.W)) // 实现ID + val mhartid = RegInit(0.U(XLEN.W)) // 硬件线程ID + val mconfigptr = RegInit(0.U(XLEN.W)) // 配置寄存器指针 + val mstatus_init = Wire(new Mstatus()) + mstatus_init := 0.U.asTypeOf(new Mstatus()) + mstatus_init.uxl := 2.U + val mstatus = RegInit(mstatus_init) // 状态寄存器 + val misa_init = Wire(new Misa()) + misa_init := 0.U.asTypeOf(new Misa()) + misa_init.mxl := 2.U + misa_init.extensions := "h101100".U + val misa = RegInit(misa_init) // ISA寄存器 + val mie = RegInit(0.U.asTypeOf(new Mie())) // 中断使能寄存器 + val mtvec = RegInit(0.U.asTypeOf(new Mtvec())) // 中断向量基址寄存器 + val mcounteren = RegInit(0.U(XLEN.W)) // 计数器使能寄存器 + val mscratch = RegInit(0.U(XLEN.W)) // 临时寄存器 + val mepc = RegInit(0.U(XLEN.W)) // 异常程序计数器 + val mcause = RegInit(0.U.asTypeOf(new Mcause())) // 异常原因寄存器 + val mtval = RegInit(0.U(XLEN.W)) // 异常值寄存器 + val mip = RegInit(0.U.asTypeOf(new Mip())) // 中断挂起寄存器 + val mcycle = cycle // 时钟周期计数器 + val minstret = instret // 指令计数器 -// // entrylo0 register (2,0) -// val csr_entrylo0 = RegInit(0.U.asTypeOf(new CsrEntryLo())) - -// // entrylo1 register (3,0) -// val csr_entrylo1 = RegInit(0.U.asTypeOf(new CsrEntryLo())) - -// // context register (4,0) -// val csr_context = RegInit(0.U.asTypeOf(new CsrContext())) - -// // page mask register (5,0) -// val csr_pagemask = 0.U - -// // wired register (6,0) -// val csr_wired = RegInit(0.U.asTypeOf(new CsrWired())) - -// // badvaddr register (8,0) -// val csr_badvaddr = RegInit(0.U.asTypeOf(new CsrBadVAddr())) - -// // count register (9,0) -// val count_init = Wire(new CsrCount()) -// count_init := 0.U.asTypeOf(new CsrCount()) -// count_init.count := 1.U -// val csr_count = RegInit(count_init) - -// // entryhi register (10,0) -// val csr_entryhi = RegInit(0.U.asTypeOf(new CsrEntryHi())) - -// // compare register (11,0) -// val csr_compare = RegInit(0.U.asTypeOf(new CsrCompare())) - -// // status register (12,0) -// val status_init = Wire(new CsrStatus()) -// status_init := 0.U.asTypeOf(new CsrStatus()) -// status_init.bev := true.B -// val csr_status = RegInit(status_init) - -// // cause register (13,0) -// val csr_cause = RegInit(0.U.asTypeOf(new CsrCause())) - -// // epc register (14,0) -// val csr_epc = RegInit(0.U.asTypeOf(new CsrEpc())) - -// // prid register (15,0) -// val prid = "h_0001_8003".U - -// // ebase register (15,1) -// val ebase_init = Wire(new CsrEbase()) -// ebase_init := 0.U.asTypeOf(new CsrEbase()) -// ebase_init.fill := true.B -// val csr_ebase = RegInit(ebase_init) - -// // config register (16,0) -// val csr_config = Wire(new CsrConfig()) -// csr_config := 0.U.asTypeOf(new CsrConfig()) -// csr_config.k0 := 3.U -// csr_config.mt := 1.U -// csr_config.m := true.B - -// // config1 register (16,1) -// val csr_config1 = Wire(new CsrConfig1()) -// csr_config1 := 0.U.asTypeOf(new CsrConfig1()) -// csr_config1.il := 5.U -// csr_config1.ia := 1.U -// csr_config1.dl := 5.U -// csr_config1.da := 1.U -// csr_config1.ms := (TLB_NUM - 1).U - -// // taglo register (28,0) -// val csr_taglo = RegInit(0.U(DATA_WID.W)) - -// // taghi register (29,0) -// val csr_taghi = RegInit(0.U(DATA_WID.W)) - -// // error epc register (30,0) -// val csr_error_epc = RegInit(0.U.asTypeOf(new CsrEpc())) - -// // random register (1,0) -// csr_random.random := Mux(csr_random.random === csr_wired.wired, (TLB_NUM - 1).U, (csr_random.random - 1.U)) - -// // context register (4,0) -// when(!mem_stall && ex.flush_req) { -// when(VecInit(EX_TLBL, EX_TLBS, EX_MOD).contains(ex.excode)) { -// csr_context.badvpn2 := ex.badvaddr(31, 13) -// } -// }.elsewhen(!exe_stall) { -// when(mtc0_wen && mtc0_addr === CSR_CONTEXT_ADDR) { -// csr_context.ptebase := mtc0_wdata.asTypeOf(new CsrContext()).ptebase -// } -// } - -// // wired register (6,0) -// when(!exe_stall) { -// when(mtc0_wen && mtc0_addr === CSR_WIRED_ADDR) { -// csr_wired.wired := mtc0_wdata.asTypeOf(new CsrWired()).wired -// csr_random.random := (TLB_NUM - 1).U -// } -// } - -// // badvaddr register (8,0) -// when(!mem_stall && ex.flush_req) { -// when(VecInit(EX_ADEL, EX_TLBL, EX_ADES, EX_TLBS, EX_MOD).contains(ex.excode)) { -// csr_badvaddr.badvaddr := ex.badvaddr -// } -// } - -// // count register (9,0) -// val tick = RegInit(false.B) -// tick := !tick -// when(tick) { -// csr_count.count := csr_count.count + 1.U -// } -// when(!exe_stall) { -// when(mtc0_wen && mtc0_addr === CSR_COUNT_ADDR) { -// csr_count.count := mtc0_wdata.asTypeOf(new CsrCount()).count -// } -// } - -// // entryhi register (10,0) -// when(!mem_stall && ex.flush_req) { -// when(VecInit(EX_TLBL, EX_TLBS, EX_MOD).contains(ex.excode)) { -// csr_entryhi.vpn2 := ex.badvaddr(31, 13) -// } -// }.elsewhen(!exe_stall) { -// when(mtc0_wen && mtc0_addr === CSR_ENTRYHI_ADDR) { -// val wdata = mtc0_wdata.asTypeOf(new CsrEntryHi()) -// csr_entryhi.asid := wdata.asid -// csr_entryhi.vpn2 := wdata.vpn2 -// } -// } - -// // compare register (11,0) -// when(!exe_stall) { -// when(mtc0_wen && mtc0_addr === CSR_COMPARE_ADDR) { -// csr_compare.compare := mtc0_wdata.asTypeOf(new CsrCompare()).compare -// } -// } - -// // status register (12,0) -// when(!mem_stall && ex.eret) { -// when(csr_status.erl) { -// csr_status.erl := false.B -// }.otherwise { -// csr_status.exl := false.B -// } -// }.elsewhen(!mem_stall && ex.flush_req) { -// csr_status.exl := true.B -// }.elsewhen(!exe_stall) { -// when(mtc0_wen && mtc0_addr === CSR_STATUS_ADDR) { -// val wdata = mtc0_wdata.asTypeOf(new CsrStatus()) -// csr_status.cu0 := wdata.cu0 -// csr_status.ie := wdata.ie -// csr_status.exl := wdata.exl -// csr_status.erl := wdata.erl -// csr_status.um := wdata.um -// csr_status.im := wdata.im -// csr_status.bev := wdata.bev -// } -// } - -// // cause register (13,0) -// csr_cause.ip := Cat( -// csr_cause.ip(7) || csr_compare.compare === csr_count.count || io.ext_int(5), // TODO:此处的ext_int可能不对 -// io.ext_int(4, 0), -// csr_cause.ip(1, 0) -// ) -// when(!mem_stall && ex.flush_req && !ex.eret) { -// when(!csr_status.exl) { -// csr_cause.bd := ex.bd -// } -// csr_cause.excode := MuxLookup(ex.excode, csr_cause.excode)( -// Seq( -// EX_NO -> EXC_NO, -// EX_INT -> EXC_INT, -// EX_MOD -> EXC_MOD, -// EX_TLBL -> EXC_TLBL, -// EX_TLBS -> EXC_TLBS, -// EX_ADEL -> EXC_ADEL, -// EX_ADES -> EXC_ADES, -// EX_SYS -> EXC_SYS, -// EX_BP -> EXC_BP, -// EX_RI -> EXC_RI, -// EX_CPU -> EXC_CPU, -// EX_OV -> EXC_OV -// ) -// ) -// }.elsewhen(!exe_stall) { -// when(mtc0_wen) { -// when(mtc0_addr === CSR_COMPARE_ADDR) { -// csr_cause.ip := Cat(false.B, csr_cause.ip(6, 0)) -// }.elsewhen(mtc0_addr === CSR_CAUSE_ADDR) { -// val wdata = mtc0_wdata.asTypeOf(new CsrCause()) -// csr_cause.ip := Cat( -// csr_cause.ip(7, 2), -// wdata.ip(1, 0) -// ) -// csr_cause.iv := wdata.iv -// } -// } -// } - -// // epc register (14,0) -// when(!mem_stall && ex.flush_req) { -// when(!csr_status.exl) { -// csr_epc.epc := Mux(ex.bd, pc - 4.U, pc) -// } -// }.elsewhen(!exe_stall) { -// when(mtc0_wen && mtc0_addr === CSR_EPC_ADDR) { -// csr_epc.epc := mtc0_wdata.asTypeOf(new CsrEpc()).epc -// } -// } - -// // ebase register (15,1) -// when(!exe_stall) { -// when(mtc0_wen && mtc0_addr === CSR_EBASE_ADDR) { -// csr_ebase.ebase := mtc0_wdata.asTypeOf(new CsrEbase()).ebase -// } -// } - -// // taglo register (28,0) -// when(!exe_stall) { -// when(mtc0_wen && mtc0_addr === CSR_TAGLO_ADDR) { -// csr_taglo := mtc0_wdata -// } -// } - -// // taghi register (29,0) -// when(!exe_stall) { -// when(mtc0_wen && mtc0_addr === CSR_TAGHI_ADDR) { -// csr_taghi := mtc0_wdata -// } -// } - -// // error epc register (30,0) -// when(!exe_stall) { -// when(mtc0_wen && mtc0_addr === CSR_ERROR_EPC_ADDR) { -// csr_error_epc.epc := mtc0_wdata.asTypeOf(new CsrEpc()).epc -// } -// } - -// for (i <- 0 until config.fuNum) { -// io.executeUnit.out.csr_rdata(i) := MuxLookup(io.executeUnit.in.inst_info(i).csr_addr, 0.U)( -// Seq( -// CSR_INDEX_ADDR -> csr_index.asUInt, -// CSR_RANDOM_ADDR -> csr_random.asUInt, -// CSR_ENTRYLO0_ADDR -> csr_entrylo0.asUInt, -// CSR_ENTRYLO1_ADDR -> csr_entrylo1.asUInt, -// CSR_CONTEXT_ADDR -> csr_context.asUInt, -// CSR_PAGE_MASK_ADDR -> csr_pagemask, -// CSR_WIRED_ADDR -> csr_wired.asUInt, -// CSR_BADV_ADDR -> csr_badvaddr.asUInt, -// CSR_COUNT_ADDR -> csr_count.asUInt, -// CSR_ENTRYHI_ADDR -> csr_entryhi.asUInt, -// CSR_COMPARE_ADDR -> csr_compare.asUInt, -// CSR_STATUS_ADDR -> csr_status.asUInt, -// CSR_CAUSE_ADDR -> csr_cause.asUInt, -// CSR_EPC_ADDR -> csr_epc.asUInt, -// CSR_PRID_ADDR -> prid, -// CSR_EBASE_ADDR -> csr_ebase.asUInt, -// CSR_CONFIG_ADDR -> csr_config.asUInt, -// CSR_CONFIG1_ADDR -> csr_config1.asUInt, -// CSR_TAGLO_ADDR -> csr_taglo, -// CSR_TAGHI_ADDR -> csr_taghi, -// CSR_ERROR_EPC_ADDR -> csr_error_epc.asUInt -// ) -// ) -// } -// io.decoderUnit.cause_ip := csr_cause.ip -// io.decoderUnit.status_im := csr_status.im -// io.decoderUnit.kernel_mode := (csr_status.exl && !(ex.eret && csr_status.erl)) || -// (csr_status.erl && !ex.eret) || -// !csr_status.um || -// (ex.flush_req && !ex.eret) -// io.decoderUnit.access_allowed := io.decoderUnit.kernel_mode || csr_status.cu0 -// io.decoderUnit.intterupt_allowed := csr_status.ie && !csr_status.exl && !csr_status.erl - -// io.executeUnit.out.debug.csr_cause := csr_cause.asUInt -// io.executeUnit.out.debug.csr_count := csr_count.asUInt -// io.executeUnit.out.debug.csr_random := csr_random.asUInt - -// val trap_base = Mux( -// csr_status.bev, -// "hbfc00200".U(PC_WID.W), -// csr_ebase.asUInt -// ) -// io.memoryUnit.out.flush := false.B -// io.memoryUnit.out.flush_pc := 0.U -// when(ex.eret) { -// io.memoryUnit.out.flush := true.B && !io.ctrl.mem_stall -// io.memoryUnit.out.flush_pc := Mux(csr_status.erl, csr_error_epc.epc, csr_epc.epc) -// }.elsewhen(ex.flush_req) { -// io.memoryUnit.out.flush := true.B && !io.ctrl.mem_stall -// io.memoryUnit.out.flush_pc := Mux( -// csr_status.exl, -// trap_base + "h180".U, -// trap_base + "h200".U -// ) -// } -// } + val tselect = RegInit(1.U(XLEN.W)) // 跟踪寄存器选择寄存器 + val tdata1 = RegInit(0.U(XLEN.W)) // 跟踪寄存器数据1寄存器 +} diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala index 4717cbb..3df5f09 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala @@ -37,9 +37,9 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module { val fu = Module(new Fu()).io val accessMemCtrl = Module(new ExeAccessMemCtrl()).io - io.ctrl.inst(0).mem_wreg := io.executeStage.inst0.inst_info.mem_wreg + io.ctrl.inst(0).mem_wreg := io.executeStage.inst0.inst_info.mem_wreg io.ctrl.inst(0).reg_waddr := io.executeStage.inst0.inst_info.reg_waddr - io.ctrl.inst(1).mem_wreg := io.executeStage.inst1.inst_info.mem_wreg + io.ctrl.inst(1).mem_wreg := io.executeStage.inst1.inst_info.mem_wreg io.ctrl.inst(1).reg_waddr := io.executeStage.inst1.inst_info.reg_waddr io.ctrl.branch := io.ctrl.allow_to_go && (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail) @@ -94,7 +94,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module { Seq( (fu.branch.pred_fail && fu.branch.branch) -> io.executeStage.inst0.jb_info.branch_target, (fu.branch.pred_fail && !fu.branch.branch) -> (io.executeStage.inst0.pc + 4.U), - (io.executeStage.inst0.jb_info.jump_regiser) -> io.executeStage.inst0.src_info.src1_data + (io.executeStage.inst0.jb_info.jump_regiser) -> (io.executeStage.inst0.src_info.src1_data + io.executeStage.inst0.src_info.src2_data) ) ) diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala index 8c73840..0f0f343 100644 --- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala +++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala @@ -1,103 +1,94 @@ -// package cpu.pipeline.memory +package cpu.pipeline.memory -// import chisel3._ -// import chisel3.util._ -// import cpu.defines._ -// import cpu.defines.Const._ -// import cpu.CpuConfig -// import cpu.pipeline.decoder.RegWrite -// import cpu.pipeline.execute.CsrMemoryUnit -// import cpu.pipeline.writeback.MemoryUnitWriteBackUnit +import chisel3._ +import chisel3.util._ +import cpu.defines._ +import cpu.defines.Const._ +import cpu.CpuConfig +import cpu.pipeline.decoder.RegWrite +import cpu.pipeline.execute.CsrMemoryUnit +import cpu.pipeline.writeback.MemoryUnitWriteBackUnit -// class MemoryUnit(implicit val config: CpuConfig) extends Module { -// val io = IO(new Bundle { -// val ctrl = new MemoryCtrl() -// val memoryStage = Input(new ExecuteUnitMemoryUnit()) -// val fetchUnit = Output(new Bundle { -// val flush = Bool() -// val flush_pc = UInt(PC_WID.W) -// }) -// val decoderUnit = Output(Vec(config.fuNum, new RegWrite())) -// val csr = Flipped(new CsrMemoryUnit()) -// val writeBackStage = Output(new MemoryUnitWriteBackUnit()) -// val dataMemory = new Bundle { -// val in = Input(new Bundle { -// val rdata = UInt(DATA_WID.W) -// }) -// val out = Output(new Bundle { -// val en = Bool() -// val rlen = UInt(2.W) -// val wen = UInt(4.W) -// val addr = UInt(DATA_ADDR_WID.W) -// val wdata = UInt(DATA_WID.W) -// }) -// } -// }) +class MemoryUnit(implicit val config: CpuConfig) extends Module { + val io = IO(new Bundle { + val ctrl = new MemoryCtrl() + val memoryStage = Input(new ExecuteUnitMemoryUnit()) + val fetchUnit = Output(new Bundle { + val flush = Bool() + val flush_pc = UInt(PC_WID.W) + }) + val decoderUnit = Output(Vec(config.fuNum, new RegWrite())) + val csr = Flipped(new CsrMemoryUnit()) + val writeBackStage = Output(new MemoryUnitWriteBackUnit()) + val dataMemory = new Bundle { + val in = Input(new Bundle { + val rdata = UInt(DATA_WID.W) + }) + val out = Output(new Bundle { + val en = Bool() + val rlen = UInt(2.W) + val wen = UInt(4.W) + val addr = UInt(DATA_ADDR_WID.W) + val wdata = UInt(DATA_WID.W) + }) + } + }) -// val dataMemoryAccess = Module(new DataMemoryAccess()).io -// dataMemoryAccess.memoryUnit.in.mem_en := io.memoryStage.inst0.mem.en -// dataMemoryAccess.memoryUnit.in.inst_info := io.memoryStage.inst0.mem.inst_info -// dataMemoryAccess.memoryUnit.in.mem_wdata := io.memoryStage.inst0.mem.wdata -// dataMemoryAccess.memoryUnit.in.mem_addr := io.memoryStage.inst0.mem.addr -// dataMemoryAccess.memoryUnit.in.mem_sel := io.memoryStage.inst0.mem.sel -// dataMemoryAccess.memoryUnit.in.ex(0) := io.memoryStage.inst0.ex -// dataMemoryAccess.memoryUnit.in.ex(1) := io.memoryStage.inst1.ex -// dataMemoryAccess.dataMemory.in.rdata := io.dataMemory.in.rdata -// dataMemoryAccess.memoryUnit.in.llbit := io.memoryStage.inst0.mem.llbit -// io.dataMemory.out := dataMemoryAccess.dataMemory.out + val dataMemoryAccess = Module(new DataMemoryAccess()).io + dataMemoryAccess.memoryUnit.in.mem_en := io.memoryStage.inst0.mem.en + dataMemoryAccess.memoryUnit.in.inst_info := io.memoryStage.inst0.mem.inst_info + dataMemoryAccess.memoryUnit.in.mem_wdata := io.memoryStage.inst0.mem.wdata + dataMemoryAccess.memoryUnit.in.mem_addr := io.memoryStage.inst0.mem.addr + dataMemoryAccess.memoryUnit.in.mem_sel := io.memoryStage.inst0.mem.sel + dataMemoryAccess.memoryUnit.in.ex(0) := io.memoryStage.inst0.ex + dataMemoryAccess.memoryUnit.in.ex(1) := io.memoryStage.inst1.ex + dataMemoryAccess.dataMemory.in.rdata := io.dataMemory.in.rdata + io.dataMemory.out := dataMemoryAccess.dataMemory.out -// io.decoderUnit(0).wen := io.writeBackStage.inst0.inst_info.reg_wen -// io.decoderUnit(0).waddr := io.writeBackStage.inst0.inst_info.reg_waddr -// io.decoderUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata -// io.decoderUnit(1).wen := io.writeBackStage.inst1.inst_info.reg_wen -// io.decoderUnit(1).waddr := io.writeBackStage.inst1.inst_info.reg_waddr -// io.decoderUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata + io.decoderUnit(0).wen := io.writeBackStage.inst0.inst_info.reg_wen + io.decoderUnit(0).waddr := io.writeBackStage.inst0.inst_info.reg_waddr + io.decoderUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata + io.decoderUnit(1).wen := io.writeBackStage.inst1.inst_info.reg_wen + io.decoderUnit(1).waddr := io.writeBackStage.inst1.inst_info.reg_waddr + io.decoderUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata -// io.writeBackStage.inst0.pc := io.memoryStage.inst0.pc -// io.writeBackStage.inst0.inst_info := io.memoryStage.inst0.inst_info -// io.writeBackStage.inst0.rd_info.wdata := Mux( -// io.writeBackStage.inst0.inst_info.mem_wreg, -// dataMemoryAccess.memoryUnit.out.rdata, -// io.memoryStage.inst0.rd_info.wdata, -// ) -// io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex -// io.writeBackStage.inst0.ex.excode := MuxCase( -// io.memoryStage.inst0.ex.excode, -// Seq( -// (io.memoryStage.inst0.ex.excode =/= EX_NO) -> io.memoryStage.inst0.ex.excode, -// ), -// ) -// io.writeBackStage.inst0.ex.flush_req := io.memoryStage.inst0.ex.flush_req || io.writeBackStage.inst0.ex.excode =/= EX_NO -// io.writeBackStage.inst0.csr := io.memoryStage.inst0.csr + io.writeBackStage.inst0.pc := io.memoryStage.inst0.pc + io.writeBackStage.inst0.inst_info := io.memoryStage.inst0.inst_info + io.writeBackStage.inst0.rd_info.wdata := Mux( + io.writeBackStage.inst0.inst_info.mem_wreg, + dataMemoryAccess.memoryUnit.out.rdata, + io.memoryStage.inst0.rd_info.wdata + ) + io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex + io.writeBackStage.inst0.ex.excode := io.memoryStage.inst0.ex.excode -// io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc -// io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info -// io.writeBackStage.inst1.rd_info.wdata := Mux( -// io.writeBackStage.inst1.inst_info.mem_wreg, -// dataMemoryAccess.memoryUnit.out.rdata, -// io.memoryStage.inst1.rd_info.wdata, -// ) -// io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex -// io.writeBackStage.inst1.ex.excode := MuxCase( -// io.memoryStage.inst1.ex.excode, -// Seq( -// (io.memoryStage.inst1.ex.excode =/= EX_NO) -> io.memoryStage.inst1.ex.excode, -// ), -// ) -// io.writeBackStage.inst1.ex.flush_req := io.memoryStage.inst1.ex.flush_req || io.writeBackStage.inst1.ex.excode =/= EX_NO + io.writeBackStage.inst0.ex.flush_req := io.memoryStage.inst0.ex.flush_req || io.writeBackStage.inst0.ex.excode.asUInt.orR + io.writeBackStage.inst0.csr := io.memoryStage.inst0.csr -// io.csr.in.inst(0).pc := io.writeBackStage.inst0.pc -// io.csr.in.inst(0).ex := io.writeBackStage.inst0.ex -// io.csr.in.inst(1).pc := io.writeBackStage.inst1.pc -// io.csr.in.inst(1).ex := io.writeBackStage.inst1.ex + io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc + io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info + io.writeBackStage.inst1.rd_info.wdata := Mux( + io.writeBackStage.inst1.inst_info.mem_wreg, + dataMemoryAccess.memoryUnit.out.rdata, + io.memoryStage.inst1.rd_info.wdata + ) + io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex + io.writeBackStage.inst1.ex.excode := io.memoryStage.inst1.ex.excode -// io.fetchUnit.flush := Mux( -// io.csr.out.flush, -// io.csr.out.flush, -// io.writeBackStage.inst0.inst_info.op === EXE_MTC0 && io.ctrl.allow_to_go, -// ) -// io.fetchUnit.flush_pc := Mux(io.csr.out.flush, io.csr.out.flush_pc, io.writeBackStage.inst0.pc + 4.U) + io.writeBackStage.inst1.ex.flush_req := io.memoryStage.inst1.ex.flush_req || io.writeBackStage.inst1.ex.excode.asUInt.orR -// io.ctrl.flush_req := io.fetchUnit.flush -// io.ctrl.eret := io.writeBackStage.inst0.ex.eret -// } + io.csr.in.inst(0).pc := io.writeBackStage.inst0.pc + io.csr.in.inst(0).ex := io.writeBackStage.inst0.ex + io.csr.in.inst(1).pc := io.writeBackStage.inst1.pc + io.csr.in.inst(1).ex := io.writeBackStage.inst1.ex + + io.fetchUnit.flush := Mux( + io.csr.out.flush, + io.csr.out.flush, + io.writeBackStage.inst0.inst_info.op === EXE_MTC0 && io.ctrl.allow_to_go + ) + io.fetchUnit.flush_pc := Mux(io.csr.out.flush, io.csr.out.flush_pc, io.writeBackStage.inst0.pc + 4.U) + + io.ctrl.flush_req := io.fetchUnit.flush + io.ctrl.eret := io.writeBackStage.inst0.ex.eret +}