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fix(dcache): 修改stall逻辑

This commit is contained in:
Liphen 2023-11-27 15:22:49 +08:00
parent 53860c99c6
commit b30026d57c
3 changed files with 13 additions and 6 deletions
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2
chisel/playground/src/Core.scala
View File

@ -123,7 +123,7 @@ class Core(implicit val config: CpuConfig) extends Module {
memoryUnit.dataMemory.in.rdata := io.data.rdata memoryUnit.dataMemory.in.rdata := io.data.rdata
io.data.en := memoryUnit.dataMemory.out.en io.data.en := memoryUnit.dataMemory.out.en
io.data.size := memoryUnit.dataMemory.out.rlen io.data.size := memoryUnit.dataMemory.out.rlen
io.data.write := memoryUnit.dataMemory.out.wen io.data.wen := memoryUnit.dataMemory.out.wen
io.data.wdata := memoryUnit.dataMemory.out.wdata io.data.wdata := memoryUnit.dataMemory.out.wdata
io.data.addr := memoryUnit.dataMemory.out.addr io.data.addr := memoryUnit.dataMemory.out.addr

11
chisel/playground/src/cache/DCache.scala vendored
View File

@ -77,9 +77,16 @@ class DCache(implicit config: CpuConfig) extends Module {
val saved_rdata = RegInit(0.U(DATA_WID.W)) val saved_rdata = RegInit(0.U(DATA_WID.W))
val acc_err = RegInit(false.B) val acc_err = RegInit(false.B)
io.cpu.rdata := saved_rdata io.cpu.rdata := saved_rdata
io.cpu.dcache_stall := Mux(status === s_idle, io.cpu.en, status =/= s_save)
io.cpu.acc_err := acc_err io.cpu.acc_err := acc_err
val mmio_read_stall = !io.cpu.wen.orR
val mmio_write_stall = io.cpu.wen.orR && !io.axi.w.ready
val cached_stall = false.B
io.cpu.dcache_stall := Mux(
status === s_idle,
Mux(io.cpu.en, (cached_stall || mmio_read_stall || mmio_write_stall), io.cpu.fence_i),
status =/= s_save
)
switch(status) { switch(status) {
is(s_idle) { is(s_idle) {
acc_err := false.B acc_err := false.B
@ -88,7 +95,7 @@ class DCache(implicit config: CpuConfig) extends Module {
acc_err := true.B acc_err := true.B
status := s_save status := s_save
}.otherwise { }.otherwise {
when(io.cpu.write) { when(io.cpu.wen) {
awaddr := io.cpu.addr(31, 0) awaddr := io.cpu.addr(31, 0)
awsize := Cat(false.B, io.cpu.size) awsize := Cat(false.B, io.cpu.size)
awvalid := true.B awvalid := true.B

2
chisel/playground/src/defines/Bundles.scala
View File

@ -126,7 +126,7 @@ class Cache_DCache extends Bundle {
val addr = Output(UInt(DATA_ADDR_WID.W)) val addr = Output(UInt(DATA_ADDR_WID.W))
val size = Output(UInt(2.W)) val size = Output(UInt(2.W))
val en = Output(Bool()) val en = Output(Bool())
val write = Output(Bool()) val wen = Output(Bool())
val wdata = Output(UInt(XLEN.W)) val wdata = Output(UInt(XLEN.W))
val cpu_ready = Output(Bool()) val cpu_ready = Output(Bool())
val fence_i = Output(Bool()) val fence_i = Output(Bool())