From b30026d57c1cd8e2a4ceda33085cce54ec7b6398 Mon Sep 17 00:00:00 2001 From: Liphen Date: Mon, 27 Nov 2023 15:22:49 +0800 Subject: [PATCH] =?UTF-8?q?fix(dcache):=20=E4=BF=AE=E6=94=B9stall=E9=80=BB?= =?UTF-8?q?=E8=BE=91?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/Core.scala | 2 +- chisel/playground/src/cache/DCache.scala | 15 +++++++++++---- chisel/playground/src/defines/Bundles.scala | 2 +- 3 files changed, 13 insertions(+), 6 deletions(-) diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala index 1556c9f..c882dc3 100644 --- a/chisel/playground/src/Core.scala +++ b/chisel/playground/src/Core.scala @@ -123,7 +123,7 @@ class Core(implicit val config: CpuConfig) extends Module { memoryUnit.dataMemory.in.rdata := io.data.rdata io.data.en := memoryUnit.dataMemory.out.en io.data.size := memoryUnit.dataMemory.out.rlen - io.data.write := memoryUnit.dataMemory.out.wen + io.data.wen := memoryUnit.dataMemory.out.wen io.data.wdata := memoryUnit.dataMemory.out.wdata io.data.addr := memoryUnit.dataMemory.out.addr diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala index dc806b0..0a09ef9 100644 --- a/chisel/playground/src/cache/DCache.scala +++ b/chisel/playground/src/cache/DCache.scala @@ -76,10 +76,17 @@ class DCache(implicit config: CpuConfig) extends Module { val saved_rdata = RegInit(0.U(DATA_WID.W)) val acc_err = RegInit(false.B) - io.cpu.rdata := saved_rdata - io.cpu.dcache_stall := Mux(status === s_idle, io.cpu.en, status =/= s_save) - io.cpu.acc_err := acc_err + io.cpu.rdata := saved_rdata + io.cpu.acc_err := acc_err + val mmio_read_stall = !io.cpu.wen.orR + val mmio_write_stall = io.cpu.wen.orR && !io.axi.w.ready + val cached_stall = false.B + io.cpu.dcache_stall := Mux( + status === s_idle, + Mux(io.cpu.en, (cached_stall || mmio_read_stall || mmio_write_stall), io.cpu.fence_i), + status =/= s_save + ) switch(status) { is(s_idle) { acc_err := false.B @@ -88,7 +95,7 @@ class DCache(implicit config: CpuConfig) extends Module { acc_err := true.B status := s_save }.otherwise { - when(io.cpu.write) { + when(io.cpu.wen) { awaddr := io.cpu.addr(31, 0) awsize := Cat(false.B, io.cpu.size) awvalid := true.B diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala index 42e2dca..573e761 100644 --- a/chisel/playground/src/defines/Bundles.scala +++ b/chisel/playground/src/defines/Bundles.scala @@ -126,7 +126,7 @@ class Cache_DCache extends Bundle { val addr = Output(UInt(DATA_ADDR_WID.W)) val size = Output(UInt(2.W)) val en = Output(Bool()) - val write = Output(Bool()) + val wen = Output(Bool()) val wdata = Output(UInt(XLEN.W)) val cpu_ready = Output(Bool()) val fence_i = Output(Bool())