简单重构wb stage级接口
This commit is contained in:
Liphen
parent
2c63e880ea
commit
b13ff2377c
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@ -22,7 +22,7 @@ class JumpBranchInfo extends Bundle {
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val update_pht_index = UInt(XLEN.W)
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}
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class DecodeUnitExecuteUnit(implicit cpuConfig: CpuConfig) extends Bundle {
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class DecodeUnitExecuteUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
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val inst = Vec(cpuConfig.commitNum, new IdExeInfo())
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val jump_branch_info = new JumpBranchInfo()
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}
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@ -136,10 +136,8 @@ class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module {
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io.memoryStage.inst(i).rd_info.wdata(FuType.bru) := io.executeStage.inst(i).pc + 4.U
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io.memoryStage.inst(i).rd_info.wdata(FuType.mdu) := fu.inst(i).result.mdu
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io.memoryStage.inst(i).rd_info.wdata(FuType.csr) := io.csr.out.rdata
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val has_ex0 =
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(HasExcInt(io.executeStage.inst(i).ex)) && io.executeStage.inst(i).info.valid
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io.memoryStage.inst(i).ex := Mux(
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has_ex0,
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(HasExcInt(io.executeStage.inst(i).ex)) && io.executeStage.inst(i).info.valid,
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io.executeStage.inst(i).ex,
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MuxLookup(io.executeStage.inst(i).info.fusel, io.executeStage.inst(i).ex)(
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Seq(
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@ -147,11 +145,9 @@ class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module {
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)
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)
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)
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io.memoryStage
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.inst(i)
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.ex
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.exception(instrAddrMisaligned) := io.executeStage.inst(i).ex.exception(instrAddrMisaligned) ||
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io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR
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io.memoryStage.inst(i).ex.exception(instrAddrMisaligned) :=
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io.executeStage.inst(i).ex.exception(instrAddrMisaligned) ||
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io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR
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io.memoryStage.inst(i).ex.tval(instrAddrMisaligned) := Mux(
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io.executeStage.inst(i).ex.exception(instrAddrMisaligned),
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io.executeStage.inst(i).ex.tval(instrAddrMisaligned),
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@ -63,7 +63,7 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
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lsu.memoryUnit.in.allow_to_go := io.ctrl.allow_to_go
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val csr_sel =
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HasExcInt(io.writeBackStage.inst0.ex) || !HasExcInt(io.writeBackStage.inst1.ex)
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HasExcInt(io.writeBackStage.inst(0).ex) || !HasExcInt(io.writeBackStage.inst(1).ex)
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io.csr.in.pc := MuxCase(
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0.U,
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@ -75,8 +75,8 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
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io.csr.in.ex := MuxCase(
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0.U.asTypeOf(new ExceptionInfo()),
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Seq(
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(io.ctrl.allow_to_go && csr_sel) -> io.writeBackStage.inst0.ex,
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(io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst1.ex
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(io.ctrl.allow_to_go && csr_sel) -> io.writeBackStage.inst(0).ex,
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(io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst(1).ex
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)
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)
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io.csr.in.info := MuxCase(
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@ -93,30 +93,30 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
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lsu.memoryUnit.in.lr := io.csr.out.lr
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lsu.memoryUnit.in.lr_addr := io.csr.out.lr_addr
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io.decodeUnit(0).wen := io.writeBackStage.inst0.info.reg_wen
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io.decodeUnit(0).waddr := io.writeBackStage.inst0.info.reg_waddr
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io.decodeUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.info.fusel)
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io.decodeUnit(1).wen := io.writeBackStage.inst1.info.reg_wen
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io.decodeUnit(1).waddr := io.writeBackStage.inst1.info.reg_waddr
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io.decodeUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.info.fusel)
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io.decodeUnit(0).wen := io.writeBackStage.inst(0).info.reg_wen
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io.decodeUnit(0).waddr := io.writeBackStage.inst(0).info.reg_waddr
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io.decodeUnit(0).wdata := io.writeBackStage.inst(0).rd_info.wdata(io.writeBackStage.inst(0).info.fusel)
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io.decodeUnit(1).wen := io.writeBackStage.inst(1).info.reg_wen
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io.decodeUnit(1).waddr := io.writeBackStage.inst(1).info.reg_waddr
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io.decodeUnit(1).wdata := io.writeBackStage.inst(1).rd_info.wdata(io.writeBackStage.inst(1).info.fusel)
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io.writeBackStage.inst0.pc := io.memoryStage.inst(0).pc
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io.writeBackStage.inst0.info := io.memoryStage.inst(0).info
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io.writeBackStage.inst0.rd_info.wdata := io.memoryStage.inst(0).rd_info.wdata
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io.writeBackStage.inst0.rd_info.wdata(FuType.lsu) := lsu.memoryUnit.out.rdata
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io.writeBackStage.inst0.ex := Mux(
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io.writeBackStage.inst(0).pc := io.memoryStage.inst(0).pc
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io.writeBackStage.inst(0).info := io.memoryStage.inst(0).info
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io.writeBackStage.inst(0).rd_info.wdata := io.memoryStage.inst(0).rd_info.wdata
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io.writeBackStage.inst(0).rd_info.wdata(FuType.lsu) := lsu.memoryUnit.out.rdata
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io.writeBackStage.inst(0).ex := Mux(
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mem_sel(0),
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lsu.memoryUnit.out.ex,
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io.memoryStage.inst(0).ex
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)
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io.writeBackStage.inst1.pc := io.memoryStage.inst(1).pc
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io.writeBackStage.inst1.info := io.memoryStage.inst(1).info
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io.writeBackStage.inst1.info.valid := io.memoryStage.inst(1).info.valid &&
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io.writeBackStage.inst(1).pc := io.memoryStage.inst(1).pc
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io.writeBackStage.inst(1).info := io.memoryStage.inst(1).info
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io.writeBackStage.inst(1).info.valid := io.memoryStage.inst(1).info.valid &&
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!(io.fetchUnit.flush && csr_sel) // 指令0导致flush时，不应该提交指令1
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io.writeBackStage.inst1.rd_info.wdata := io.memoryStage.inst(1).rd_info.wdata
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io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := lsu.memoryUnit.out.rdata
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io.writeBackStage.inst1.ex := Mux(
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io.writeBackStage.inst(1).rd_info.wdata := io.memoryStage.inst(1).rd_info.wdata
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io.writeBackStage.inst(1).rd_info.wdata(FuType.lsu) := lsu.memoryUnit.out.rdata
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io.writeBackStage.inst(1).ex := Mux(
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mem_sel(1),
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lsu.memoryUnit.out.ex,
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io.memoryStage.inst(1).ex
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@ -6,16 +6,15 @@ import cpu.defines._
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import cpu.defines.Const._
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import cpu.CpuConfig
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class MemWbInst extends Bundle {
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class MemWbInfo extends Bundle {
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val pc = UInt(XLEN.W)
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val info = new InstInfo()
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val rd_info = new RdInfo()
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val ex = new ExceptionInfo()
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}
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class MemoryUnitWriteBackUnit extends Bundle {
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val inst0 = new MemWbInst()
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val inst1 = new MemWbInst()
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class MemoryUnitWriteBackUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
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val inst = Vec(cpuConfig.commitNum, new MemWbInfo())
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}
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class WriteBackStage(implicit val cpuConfig: CpuConfig) extends Module {
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val io = IO(new Bundle {
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@ -26,17 +25,16 @@ class WriteBackStage(implicit val cpuConfig: CpuConfig) extends Module {
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val memoryUnit = Input(new MemoryUnitWriteBackUnit())
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val writeBackUnit = Output(new MemoryUnitWriteBackUnit())
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})
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val inst0 = RegInit(0.U.asTypeOf(new MemWbInst()))
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val inst1 = RegInit(0.U.asTypeOf(new MemWbInst()))
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when(io.ctrl.clear(0)) {
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inst0 := 0.U.asTypeOf(new MemWbInst())
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inst1 := 0.U.asTypeOf(new MemWbInst())
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}.elsewhen(io.ctrl.allow_to_go) {
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inst0 := io.memoryUnit.inst0
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inst1 := io.memoryUnit.inst1
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val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new MemWbInfo())))
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for (i <- 0 until (cpuConfig.commitNum)) {
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when(io.ctrl.clear) {
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inst(i) := 0.U.asTypeOf(new MemWbInfo())
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}.elsewhen(io.ctrl.allow_to_go) {
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inst(i) := io.memoryUnit.inst(i)
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}
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}
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io.writeBackUnit.inst0 := inst0
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io.writeBackUnit.inst1 := inst1
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io.writeBackUnit.inst := inst
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}
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@ -16,34 +16,32 @@ class WriteBackUnit(implicit val cpuConfig: CpuConfig) extends Module {
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})
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io.regfile(0).wen :=
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io.writeBackStage.inst0.info.valid &&
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io.writeBackStage.inst0.info.reg_wen &&
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io.writeBackStage.inst(0).info.valid &&
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io.writeBackStage.inst(0).info.reg_wen &&
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io.ctrl.allow_to_go &&
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!(HasExcInt(io.writeBackStage.inst0.ex))
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io.regfile(0).waddr := io.writeBackStage.inst0.info.reg_waddr
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io.regfile(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.info.fusel)
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!(HasExcInt(io.writeBackStage.inst(0).ex))
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io.regfile(1).wen :=
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io.writeBackStage.inst1.info.valid &&
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io.writeBackStage.inst1.info.reg_wen &&
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io.writeBackStage.inst(1).info.valid &&
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io.writeBackStage.inst(1).info.reg_wen &&
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io.ctrl.allow_to_go &&
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!(HasExcInt(io.writeBackStage.inst0.ex)) &&
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!(HasExcInt(io.writeBackStage.inst1.ex))
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io.regfile(1).waddr := io.writeBackStage.inst1.info.reg_waddr
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io.regfile(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.info.fusel)
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!(HasExcInt(io.writeBackStage.inst(0).ex)) &&
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!(HasExcInt(io.writeBackStage.inst(1).ex))
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for (i <- 0 until (cpuConfig.commitNum)) {
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io.regfile(i).waddr := io.writeBackStage.inst(i).info.reg_waddr
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io.regfile(i).wdata := io.writeBackStage.inst(i).rd_info.wdata(io.writeBackStage.inst(i).info.fusel)
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}
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if (cpuConfig.hasCommitBuffer) {
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val buffer = Module(new CommitBuffer()).io
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buffer.enq(0).wb_pc := io.writeBackStage.inst0.pc
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buffer.enq(0).wb_rf_wen := io.writeBackStage.inst0.info.valid && io.ctrl.allow_to_go
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buffer.enq(0).wb_rf_wnum := io.regfile(0).waddr
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buffer.enq(0).wb_rf_wdata := io.regfile(0).wdata
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buffer.enq(1).wb_pc := io.writeBackStage.inst1.pc
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buffer.enq(1).wb_rf_wen := io.writeBackStage.inst1.info.valid && io.ctrl.allow_to_go
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buffer.enq(1).wb_rf_wnum := io.regfile(1).waddr
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buffer.enq(1).wb_rf_wdata := io.regfile(1).wdata
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buffer.flush := io.ctrl.do_flush
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for (i <- 0 until (cpuConfig.commitNum)) {
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buffer.enq(i).wb_pc := io.writeBackStage.inst(i).pc
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buffer.enq(i).wb_rf_wen := io.writeBackStage.inst(i).info.valid && io.ctrl.allow_to_go
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buffer.enq(i).wb_rf_wnum := io.regfile(i).waddr
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buffer.enq(i).wb_rf_wdata := io.regfile(i).wdata
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}
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buffer.flush := io.ctrl.do_flush
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io.debug.wb_pc := buffer.deq.wb_pc
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io.debug.wb_rf_wen := buffer.deq.wb_rf_wen
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io.debug.wb_rf_wnum := buffer.deq.wb_rf_wnum
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@ -51,17 +49,17 @@ class WriteBackUnit(implicit val cpuConfig: CpuConfig) extends Module {
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} else {
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io.debug.wb_pc := Mux(
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clock.asBool,
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io.writeBackStage.inst0.pc,
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io.writeBackStage.inst(0).pc,
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Mux(
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!(io.writeBackStage.inst1.info.valid && io.ctrl.allow_to_go),
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!(io.writeBackStage.inst(1).info.valid && io.ctrl.allow_to_go),
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0.U,
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io.writeBackStage.inst1.pc
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io.writeBackStage.inst(1).pc
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)
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)
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io.debug.wb_rf_wen := Mux(
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clock.asBool,
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io.writeBackStage.inst0.info.valid && io.ctrl.allow_to_go,
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io.writeBackStage.inst1.info.valid && io.ctrl.allow_to_go
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io.writeBackStage.inst(0).info.valid && io.ctrl.allow_to_go,
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io.writeBackStage.inst(1).info.valid && io.ctrl.allow_to_go
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)
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io.debug.wb_rf_wnum := Mux(
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clock.asBool,
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