diff --git a/chisel/playground/src/pipeline/execute/ExecuteStage.scala b/chisel/playground/src/pipeline/execute/ExecuteStage.scala
index 119ee1b..7add197 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteStage.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteStage.scala
@@ -22,7 +22,7 @@ class JumpBranchInfo extends Bundle {
   val update_pht_index = UInt(XLEN.W)
 }
 
-class DecodeUnitExecuteUnit(implicit cpuConfig: CpuConfig) extends Bundle {
+class DecodeUnitExecuteUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
   val inst             = Vec(cpuConfig.commitNum, new IdExeInfo())
   val jump_branch_info = new JumpBranchInfo()
 }
diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
index 0c94b31..ec3668d 100644
--- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
+++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala
@@ -136,10 +136,8 @@ class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module {
     io.memoryStage.inst(i).rd_info.wdata(FuType.bru) := io.executeStage.inst(i).pc + 4.U
     io.memoryStage.inst(i).rd_info.wdata(FuType.mdu) := fu.inst(i).result.mdu
     io.memoryStage.inst(i).rd_info.wdata(FuType.csr) := io.csr.out.rdata
-    val has_ex0 =
-      (HasExcInt(io.executeStage.inst(i).ex)) && io.executeStage.inst(i).info.valid
     io.memoryStage.inst(i).ex := Mux(
-      has_ex0,
+      (HasExcInt(io.executeStage.inst(i).ex)) && io.executeStage.inst(i).info.valid,
       io.executeStage.inst(i).ex,
       MuxLookup(io.executeStage.inst(i).info.fusel, io.executeStage.inst(i).ex)(
         Seq(
@@ -147,11 +145,9 @@ class ExecuteUnit(implicit val cpuConfig: CpuConfig) extends Module {
         )
       )
     )
-    io.memoryStage
-      .inst(i)
-      .ex
-      .exception(instrAddrMisaligned) := io.executeStage.inst(i).ex.exception(instrAddrMisaligned) ||
-    io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR
+    io.memoryStage.inst(i).ex.exception(instrAddrMisaligned) :=
+      io.executeStage.inst(i).ex.exception(instrAddrMisaligned) ||
+      io.fetchUnit.flush && io.fetchUnit.target(log2Ceil(INST_WID / 8) - 1, 0).orR
     io.memoryStage.inst(i).ex.tval(instrAddrMisaligned) := Mux(
       io.executeStage.inst(i).ex.exception(instrAddrMisaligned),
       io.executeStage.inst(i).ex.tval(instrAddrMisaligned),
diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
index ab83f4d..915c2f4 100644
--- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala
+++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala
@@ -63,7 +63,7 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
   lsu.memoryUnit.in.allow_to_go := io.ctrl.allow_to_go
 
   val csr_sel =
-    HasExcInt(io.writeBackStage.inst0.ex) || !HasExcInt(io.writeBackStage.inst1.ex)
+    HasExcInt(io.writeBackStage.inst(0).ex) || !HasExcInt(io.writeBackStage.inst(1).ex)
 
   io.csr.in.pc := MuxCase(
     0.U,
@@ -75,8 +75,8 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
   io.csr.in.ex := MuxCase(
     0.U.asTypeOf(new ExceptionInfo()),
     Seq(
-      (io.ctrl.allow_to_go && csr_sel)  -> io.writeBackStage.inst0.ex,
-      (io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst1.ex
+      (io.ctrl.allow_to_go && csr_sel)  -> io.writeBackStage.inst(0).ex,
+      (io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst(1).ex
     )
   )
   io.csr.in.info := MuxCase(
@@ -93,30 +93,30 @@ class MemoryUnit(implicit val cpuConfig: CpuConfig) extends Module {
   lsu.memoryUnit.in.lr      := io.csr.out.lr
   lsu.memoryUnit.in.lr_addr := io.csr.out.lr_addr
 
-  io.decodeUnit(0).wen   := io.writeBackStage.inst0.info.reg_wen
-  io.decodeUnit(0).waddr := io.writeBackStage.inst0.info.reg_waddr
-  io.decodeUnit(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.info.fusel)
-  io.decodeUnit(1).wen   := io.writeBackStage.inst1.info.reg_wen
-  io.decodeUnit(1).waddr := io.writeBackStage.inst1.info.reg_waddr
-  io.decodeUnit(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.info.fusel)
+  io.decodeUnit(0).wen   := io.writeBackStage.inst(0).info.reg_wen
+  io.decodeUnit(0).waddr := io.writeBackStage.inst(0).info.reg_waddr
+  io.decodeUnit(0).wdata := io.writeBackStage.inst(0).rd_info.wdata(io.writeBackStage.inst(0).info.fusel)
+  io.decodeUnit(1).wen   := io.writeBackStage.inst(1).info.reg_wen
+  io.decodeUnit(1).waddr := io.writeBackStage.inst(1).info.reg_waddr
+  io.decodeUnit(1).wdata := io.writeBackStage.inst(1).rd_info.wdata(io.writeBackStage.inst(1).info.fusel)
 
-  io.writeBackStage.inst0.pc                        := io.memoryStage.inst(0).pc
-  io.writeBackStage.inst0.info                      := io.memoryStage.inst(0).info
-  io.writeBackStage.inst0.rd_info.wdata             := io.memoryStage.inst(0).rd_info.wdata
-  io.writeBackStage.inst0.rd_info.wdata(FuType.lsu) := lsu.memoryUnit.out.rdata
-  io.writeBackStage.inst0.ex := Mux(
+  io.writeBackStage.inst(0).pc                        := io.memoryStage.inst(0).pc
+  io.writeBackStage.inst(0).info                      := io.memoryStage.inst(0).info
+  io.writeBackStage.inst(0).rd_info.wdata             := io.memoryStage.inst(0).rd_info.wdata
+  io.writeBackStage.inst(0).rd_info.wdata(FuType.lsu) := lsu.memoryUnit.out.rdata
+  io.writeBackStage.inst(0).ex := Mux(
     mem_sel(0),
     lsu.memoryUnit.out.ex,
     io.memoryStage.inst(0).ex
   )
 
-  io.writeBackStage.inst1.pc   := io.memoryStage.inst(1).pc
-  io.writeBackStage.inst1.info := io.memoryStage.inst(1).info
-  io.writeBackStage.inst1.info.valid := io.memoryStage.inst(1).info.valid &&
+  io.writeBackStage.inst(1).pc   := io.memoryStage.inst(1).pc
+  io.writeBackStage.inst(1).info := io.memoryStage.inst(1).info
+  io.writeBackStage.inst(1).info.valid := io.memoryStage.inst(1).info.valid &&
     !(io.fetchUnit.flush && csr_sel) // 指令0导致flush时，不应该提交指令1
-  io.writeBackStage.inst1.rd_info.wdata             := io.memoryStage.inst(1).rd_info.wdata
-  io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := lsu.memoryUnit.out.rdata
-  io.writeBackStage.inst1.ex := Mux(
+  io.writeBackStage.inst(1).rd_info.wdata             := io.memoryStage.inst(1).rd_info.wdata
+  io.writeBackStage.inst(1).rd_info.wdata(FuType.lsu) := lsu.memoryUnit.out.rdata
+  io.writeBackStage.inst(1).ex := Mux(
     mem_sel(1),
     lsu.memoryUnit.out.ex,
     io.memoryStage.inst(1).ex
diff --git a/chisel/playground/src/pipeline/writeback/WriteBackStage.scala b/chisel/playground/src/pipeline/writeback/WriteBackStage.scala
index 9f13054..0250044 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackStage.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackStage.scala
@@ -6,16 +6,15 @@ import cpu.defines._
 import cpu.defines.Const._
 import cpu.CpuConfig
 
-class MemWbInst extends Bundle {
+class MemWbInfo extends Bundle {
   val pc      = UInt(XLEN.W)
   val info    = new InstInfo()
   val rd_info = new RdInfo()
   val ex      = new ExceptionInfo()
 }
 
-class MemoryUnitWriteBackUnit extends Bundle {
-  val inst0 = new MemWbInst()
-  val inst1 = new MemWbInst()
+class MemoryUnitWriteBackUnit(implicit val cpuConfig: CpuConfig) extends Bundle {
+  val inst = Vec(cpuConfig.commitNum, new MemWbInfo())
 }
 class WriteBackStage(implicit val cpuConfig: CpuConfig) extends Module {
   val io = IO(new Bundle {
@@ -26,17 +25,16 @@ class WriteBackStage(implicit val cpuConfig: CpuConfig) extends Module {
     val memoryUnit    = Input(new MemoryUnitWriteBackUnit())
     val writeBackUnit = Output(new MemoryUnitWriteBackUnit())
   })
-  val inst0 = RegInit(0.U.asTypeOf(new MemWbInst()))
-  val inst1 = RegInit(0.U.asTypeOf(new MemWbInst()))
 
-  when(io.ctrl.clear(0)) {
-    inst0 := 0.U.asTypeOf(new MemWbInst())
-    inst1 := 0.U.asTypeOf(new MemWbInst())
-  }.elsewhen(io.ctrl.allow_to_go) {
-    inst0 := io.memoryUnit.inst0
-    inst1 := io.memoryUnit.inst1
+  val inst = Seq.fill(cpuConfig.commitNum)(RegInit(0.U.asTypeOf(new MemWbInfo())))
+
+  for (i <- 0 until (cpuConfig.commitNum)) {
+    when(io.ctrl.clear) {
+      inst(i) := 0.U.asTypeOf(new MemWbInfo())
+    }.elsewhen(io.ctrl.allow_to_go) {
+      inst(i) := io.memoryUnit.inst(i)
+    }
   }
 
-  io.writeBackUnit.inst0 := inst0
-  io.writeBackUnit.inst1 := inst1
+  io.writeBackUnit.inst := inst
 }
diff --git a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
index 1ea56e2..3792f4d 100644
--- a/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
+++ b/chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
@@ -16,34 +16,32 @@ class WriteBackUnit(implicit val cpuConfig: CpuConfig) extends Module {
   })
 
   io.regfile(0).wen :=
-    io.writeBackStage.inst0.info.valid &&
-      io.writeBackStage.inst0.info.reg_wen &&
+    io.writeBackStage.inst(0).info.valid &&
+      io.writeBackStage.inst(0).info.reg_wen &&
       io.ctrl.allow_to_go &&
-      !(HasExcInt(io.writeBackStage.inst0.ex))
-  io.regfile(0).waddr := io.writeBackStage.inst0.info.reg_waddr
-  io.regfile(0).wdata := io.writeBackStage.inst0.rd_info.wdata(io.writeBackStage.inst0.info.fusel)
+      !(HasExcInt(io.writeBackStage.inst(0).ex))
 
   io.regfile(1).wen :=
-    io.writeBackStage.inst1.info.valid &&
-      io.writeBackStage.inst1.info.reg_wen &&
+    io.writeBackStage.inst(1).info.valid &&
+      io.writeBackStage.inst(1).info.reg_wen &&
       io.ctrl.allow_to_go &&
-      !(HasExcInt(io.writeBackStage.inst0.ex)) &&
-      !(HasExcInt(io.writeBackStage.inst1.ex))
-  io.regfile(1).waddr := io.writeBackStage.inst1.info.reg_waddr
-  io.regfile(1).wdata := io.writeBackStage.inst1.rd_info.wdata(io.writeBackStage.inst1.info.fusel)
+      !(HasExcInt(io.writeBackStage.inst(0).ex)) &&
+      !(HasExcInt(io.writeBackStage.inst(1).ex))
+
+  for (i <- 0 until (cpuConfig.commitNum)) {
+    io.regfile(i).waddr := io.writeBackStage.inst(i).info.reg_waddr
+    io.regfile(i).wdata := io.writeBackStage.inst(i).rd_info.wdata(io.writeBackStage.inst(i).info.fusel)
+  }
 
   if (cpuConfig.hasCommitBuffer) {
     val buffer = Module(new CommitBuffer()).io
-    buffer.enq(0).wb_pc       := io.writeBackStage.inst0.pc
-    buffer.enq(0).wb_rf_wen   := io.writeBackStage.inst0.info.valid && io.ctrl.allow_to_go
-    buffer.enq(0).wb_rf_wnum  := io.regfile(0).waddr
-    buffer.enq(0).wb_rf_wdata := io.regfile(0).wdata
-    buffer.enq(1).wb_pc       := io.writeBackStage.inst1.pc
-    buffer.enq(1).wb_rf_wen   := io.writeBackStage.inst1.info.valid && io.ctrl.allow_to_go
-    buffer.enq(1).wb_rf_wnum  := io.regfile(1).waddr
-    buffer.enq(1).wb_rf_wdata := io.regfile(1).wdata
-    buffer.flush              := io.ctrl.do_flush
-
+    for (i <- 0 until (cpuConfig.commitNum)) {
+      buffer.enq(i).wb_pc       := io.writeBackStage.inst(i).pc
+      buffer.enq(i).wb_rf_wen   := io.writeBackStage.inst(i).info.valid && io.ctrl.allow_to_go
+      buffer.enq(i).wb_rf_wnum  := io.regfile(i).waddr
+      buffer.enq(i).wb_rf_wdata := io.regfile(i).wdata
+    }
+    buffer.flush         := io.ctrl.do_flush
     io.debug.wb_pc       := buffer.deq.wb_pc
     io.debug.wb_rf_wen   := buffer.deq.wb_rf_wen
     io.debug.wb_rf_wnum  := buffer.deq.wb_rf_wnum
@@ -51,17 +49,17 @@ class WriteBackUnit(implicit val cpuConfig: CpuConfig) extends Module {
   } else {
     io.debug.wb_pc := Mux(
       clock.asBool,
-      io.writeBackStage.inst0.pc,
+      io.writeBackStage.inst(0).pc,
       Mux(
-        !(io.writeBackStage.inst1.info.valid && io.ctrl.allow_to_go),
+        !(io.writeBackStage.inst(1).info.valid && io.ctrl.allow_to_go),
         0.U,
-        io.writeBackStage.inst1.pc
+        io.writeBackStage.inst(1).pc
       )
     )
     io.debug.wb_rf_wen := Mux(
       clock.asBool,
-      io.writeBackStage.inst0.info.valid && io.ctrl.allow_to_go,
-      io.writeBackStage.inst1.info.valid && io.ctrl.allow_to_go
+      io.writeBackStage.inst(0).info.valid && io.ctrl.allow_to_go,
+      io.writeBackStage.inst(1).info.valid && io.ctrl.allow_to_go
     )
     io.debug.wb_rf_wnum := Mux(
       clock.asBool,