fix(mem): 修复wstrb错误

chisel/playground/src/Core.scala

@@ -125,6 +125,7 @@ class Core(implicit val config: CpuConfig) extends Module {
   io.data.wen                    := memoryUnit.dataMemory.out.wen
   io.data.wdata                  := memoryUnit.dataMemory.out.wdata
   io.data.addr                   := memoryUnit.dataMemory.out.addr
+  io.data.wstrb                  := memoryUnit.dataMemory.out.wstrb
 
   writeBackStage.memoryUnit <> memoryUnit.writeBackStage
   writeBackStage.ctrl.allow_to_go := ctrl.writeBackUnit.allow_to_go

chisel/playground/src/cache/DCache.scala

@@ -18,24 +18,14 @@ class DCache(implicit config: CpuConfig) extends Module {
   val s_idle :: s_uncached :: s_writeback :: s_save :: Nil = Enum(4)
   val status                                               = RegInit(s_idle)
 
-  val wstrb_gen = Wire(UInt(8.W))
-  wstrb_gen := MuxLookup(io.cpu.size, "b1111_1111".U)(
-    Seq(
-      0.U -> ("b1".U << io.cpu.addr(2, 0)),
-      1.U -> ("b11".U << Cat(io.cpu.addr(2, 1), 0.U(1.W))),
-      2.U -> ("b1111".U << Cat(io.cpu.addr(2), 0.U(2.W))),
-      3.U -> ("b1111_1111".U)
-    )
-  )
-
   io.cpu.valid := status === s_save
 
   val addr_err = io.cpu.addr(63, 32).orR
 
   // default
   val awvalid = RegInit(false.B)
-  val awaddr  = RegInit(0.U(32.W))
+  val awaddr  = RegInit(0.U(AXI_ADDR_WID.W))
-  val awsize  = RegInit(0.U(3.W))
+  val awsize  = RegInit(0.U(AXI_SIZE_WID.W))
   io.axi.aw.id    := 1.U
   io.axi.aw.addr  := awaddr
   io.axi.aw.len   := 0.U
@@ -47,8 +37,8 @@ class DCache(implicit config: CpuConfig) extends Module {
   io.axi.aw.cache := 0.U
 
   val wvalid = RegInit(false.B)
-  val wdata  = RegInit(0.U(XLEN.W))
+  val wdata  = RegInit(0.U(AXI_DATA_WID.W))
-  val wstrb  = RegInit(0.U(4.W))
+  val wstrb  = RegInit(0.U(AXI_STRB_WID.W))
   io.axi.w.id    := 1.U
   io.axi.w.data  := wdata
   io.axi.w.strb  := wstrb
@@ -57,9 +47,9 @@ class DCache(implicit config: CpuConfig) extends Module {
 
   io.axi.b.ready := 1.U
 
-  val araddr  = RegInit(0.U(32.W))
+  val araddr  = RegInit(0.U(AXI_ADDR_WID.W))
-  val arsize  = RegInit(0.U(3.W))
+  val arsize  = RegInit(0.U(AXI_SIZE_WID.W))
-  val arlen   = RegInit(0.U(8.W))
+  val arlen   = RegInit(0.U(AXI_LEN_WID.W))
   val arvalid = RegInit(false.B)
   io.axi.ar.id    := 1.U
   io.axi.ar.addr  := araddr
@@ -87,6 +77,7 @@ class DCache(implicit config: CpuConfig) extends Module {
     Mux(io.cpu.en, (cached_stall || mmio_read_stall || mmio_write_stall), io.cpu.fence_i),
     status =/= s_save
   )
+
   switch(status) {
     is(s_idle) {
       acc_err := false.B
@@ -100,7 +91,7 @@ class DCache(implicit config: CpuConfig) extends Module {
             awsize  := Cat(false.B, io.cpu.size)
             awvalid := true.B
             wdata   := io.cpu.wdata
-            wstrb   := wstrb_gen
+            wstrb   := io.cpu.wstrb
             wvalid  := true.B
             status  := s_writeback
           }.otherwise {

chisel/playground/src/cache/ICache.scala

@@ -23,7 +23,7 @@ class ICache(implicit config: CpuConfig) extends Module {
 
   // default
   val arvalid = RegInit(false.B)
-  val araddr  = RegInit(0.U(32.W))
+  val araddr  = RegInit(0.U(AXI_ADDR_WID.W))
   io.axi.ar.id    := 0.U
   io.axi.ar.addr  := araddr
   io.axi.ar.len   := 0.U
@@ -36,7 +36,7 @@ class ICache(implicit config: CpuConfig) extends Module {
 
   val rready = RegInit(false.B)
   val saved = RegInit(VecInit(Seq.fill(config.instFetchNum)(0.U.asTypeOf(new Bundle {
-    val inst  = UInt(32.W)
+    val inst  = UInt(AXI_DATA_WID.W)
     val valid = Bool()
   }))))
   io.axi.r.ready := true.B

chisel/playground/src/defines/Bundles.scala

@@ -130,6 +130,7 @@ class Cache_DCache extends Bundle {
   val wdata     = Output(UInt(XLEN.W))
   val cpu_ready = Output(Bool())
   val fence_i   = Output(Bool())
+  val wstrb     = Output(UInt(AXI_STRB_WID.W))
 
   val rdata        = Input(UInt(XLEN.W))
   val valid        = Input(Bool())
@@ -141,14 +142,14 @@ class Cache_DCache extends Bundle {
 // master -> slave
 
 class AR extends Bundle {
-  val id    = Output(UInt(4.W))
+  val id    = Output(UInt(AXI_ID_WID.W))
-  val addr  = Output(UInt(32.W))
+  val addr  = Output(UInt(AXI_ADDR_WID.W))
-  val len   = Output(UInt(8.W))
+  val len   = Output(UInt(AXI_LEN_WID.W))
-  val size  = Output(UInt(3.W))
+  val size  = Output(UInt(AXI_SIZE_WID.W))
-  val burst = Output(UInt(2.W))
+  val burst = Output(UInt(AXI_BURST_WID.W))
-  val lock  = Output(UInt(2.W))
+  val lock  = Output(UInt(AXI_LOCK_WID.W))
-  val cache = Output(UInt(4.W))
+  val cache = Output(UInt(AXI_CACHE_WID.W))
-  val prot  = Output(UInt(3.W))
+  val prot  = Output(UInt(AXI_PROT_WID.W))
   val valid = Output(Bool())
 
   val ready = Input(Bool())
@@ -157,31 +158,31 @@ class AR extends Bundle {
 class R extends Bundle {
   val ready = Output(Bool())
 
-  val id    = Input(UInt(4.W))
+  val id    = Input(UInt(AXI_ID_WID.W))
-  val data  = Input(UInt(XLEN.W))
+  val data  = Input(UInt(AXI_DATA_WID.W))
-  val resp  = Input(UInt(2.W))
+  val resp  = Input(UInt(AXI_RESP_WID.W))
   val last  = Input(Bool())
   val valid = Input(Bool())
 }
 
 class AW extends Bundle {
-  val id    = Output(UInt(4.W))
+  val id    = Output(UInt(AXI_ID_WID.W))
-  val addr  = Output(UInt(32.W))
+  val addr  = Output(UInt(AXI_ADDR_WID.W))
-  val len   = Output(UInt(8.W))
+  val len   = Output(UInt(AXI_LEN_WID.W))
-  val size  = Output(UInt(3.W))
+  val size  = Output(UInt(AXI_SIZE_WID.W))
-  val burst = Output(UInt(2.W))
+  val burst = Output(UInt(AXI_BURST_WID.W))
-  val lock  = Output(UInt(2.W))
+  val lock  = Output(UInt(AXI_LOCK_WID.W))
-  val cache = Output(UInt(4.W))
+  val cache = Output(UInt(AXI_CACHE_WID.W))
-  val prot  = Output(UInt(3.W))
+  val prot  = Output(UInt(AXI_PROT_WID.W))
   val valid = Output(Bool())
 
   val ready = Input(Bool())
 }
 
 class W extends Bundle {
-  val id    = Output(UInt(4.W))
+  val id    = Output(UInt(AXI_ID_WID.W))
-  val data  = Output(UInt(XLEN.W))
+  val data  = Output(UInt(AXI_DATA_WID.W))
-  val strb  = Output(UInt(4.W))
+  val strb  = Output(UInt(AXI_STRB_WID.W))
   val last  = Output(Bool())
   val valid = Output(Bool())
 
@@ -191,8 +192,8 @@ class W extends Bundle {
 class B extends Bundle {
   val ready = Output(Bool())
 
-  val id    = Input(UInt(4.W))
+  val id    = Input(UInt(AXI_ID_WID.W))
-  val resp  = Input(UInt(2.W))
+  val resp  = Input(UInt(AXI_RESP_WID.W))
   val valid = Input(Bool())
 }
 
@@ -225,25 +226,8 @@ class AXI extends Bundle {
 }
 
 class DEBUG extends Bundle {
-  val wb_pc       = Output(UInt(32.W))
+  val wb_pc       = Output(UInt(PC_WID.W))
   val wb_rf_wen   = Output(Bool())
-  val wb_rf_wnum  = Output(UInt(5.W))
+  val wb_rf_wnum  = Output(UInt(REG_ADDR_WID.W))
-  val wb_rf_wdata = Output(UInt(32.W))
+  val wb_rf_wdata = Output(UInt(DATA_WID.W))
-}
-
-class Ctrl_Sram extends Bundle {
-  val do_flush = Output(Bool())
-}
-
-class Ctrl_Stage extends Bundle {
-  val do_flush = Output(Bool())
-  val after_ex = Output(Bool())
-}
-
-class Sram_Ctrl extends Bundle {
-  val sram_discard = Output(UInt(2.W))
-}
-
-class Pipeline_Ctrl extends Bundle {
-  val ex = Output(Bool())
 }

chisel/playground/src/defines/Const.scala

@@ -33,7 +33,7 @@ trait Constants extends CoreParameter {
   val DIV_STOP             = false.B
 
   // inst rom
-  val INST_WID      = 32
+  val INST_WID      = XLEN
   val INST_ADDR_WID = XLEN
 
   // data ram
@@ -97,6 +97,18 @@ trait AXIConst {
   val RESP_EXOKEY = 1
   val RESP_SLVERR = 2
   val RESP_DECERR = 3
+
+  val AXI_ID_WID    = 4
+  val AXI_ADDR_WID  = 32
+  val AXI_DATA_WID  = 64
+  val AXI_STRB_WID  = 8
+  val AXI_RESP_WID  = 2
+  val AXI_LEN_WID   = 8
+  val AXI_SIZE_WID  = 3
+  val AXI_BURST_WID = 2
+  val AXI_LOCK_WID  = 2
+  val AXI_CACHE_WID = 4
+  val AXI_PROT_WID  = 3
 }
 object Const extends Constants with AXIConst with HasExceptionNO
 

chisel/playground/src/pipeline/memory/DataMemoryAccess.scala

@@ -28,10 +28,11 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
       })
       val out = Output(new Bundle {
         val en    = Bool()
-        val rlen  = UInt(2.W)
+        val rlen  = UInt(AXI_LEN_WID.W)
         val wen   = Bool()
-        val addr  = UInt(DATA_ADDR_WID.W)
+        val wstrb = UInt(AXI_STRB_WID.W)
-        val wdata = UInt(DATA_WID.W)
+        val addr  = UInt(AXI_ADDR_WID.W)
+        val wdata = UInt(AXI_DATA_WID.W)
       })
     }
   })
@@ -80,7 +81,20 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
       )
     )
   }
+  def genWmask(addr: UInt, sizeEncode: UInt): UInt = {
+    LookupTree(
+      sizeEncode,
+      List(
+        "b00".U -> 0x1.U, //0001 << addr(2:0)
+        "b01".U -> 0x3.U, //0011
+        "b10".U -> 0xf.U, //1111
+        "b11".U -> 0xff.U //11111111
+      )
+    ) << addr(2, 0)
+  }
+
   io.dataMemory.out.wdata := genWdata(mem_wdata, op(1, 0))
   io.dataMemory.out.wen   := LSUOpType.isStore(op) && io.memoryUnit.in.mem_en
+  io.dataMemory.out.wstrb := genWmask(mem_addr, op(1, 0))
   io.dataMemory.out.rlen  := op(1, 0)
 }

chisel/playground/src/pipeline/memory/MemoryUnit.scala

@@ -26,10 +26,11 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
       })
       val out = Output(new Bundle {
         val en    = Bool()
-        val rlen  = UInt(2.W)
+        val rlen  = UInt(AXI_LEN_WID.W)
-        val wen   = UInt(4.W)
+        val wen   = Bool()
-        val addr  = UInt(DATA_ADDR_WID.W)
+        val addr  = UInt(AXI_ADDR_WID.W)
-        val wdata = UInt(DATA_WID.W)
+        val wdata = UInt(AXI_DATA_WID.W)
+        val wstrb = UInt(AXI_STRB_WID.W)
       })
     }
   })