增加特权指令

chisel/playground/src/CpuConfig.scala

@@ -4,8 +4,13 @@ import chisel3.util._
 
 case class CpuConfig(
   val build: Boolean = false, // 是否为build模式
+  // 指令集
   val isRV32:        Boolean = false, // 是否为RV32
-  val hasMDU:          Boolean = false, // 是否有乘除法单元
+  val hasMExtension: Boolean = false, // 是否有乘除法单元
+  // 特权模式
+  val hasSMode: Boolean = false, // 是否有S模式
+  val hasUMode: Boolean = false, // 是否有U模式
+  // 模块配置
   val hasCommitBuffer: Boolean = false, // 是否有提交缓存
   val decoderNum:      Int     = 1, // 同时访问寄存器的指令数
   val commitNum:       Int     = 1, // 同时提交的指令数

chisel/playground/src/defines/Const.scala

@@ -22,8 +22,6 @@ trait Constants extends CoreParameter {
   def WRITE_DISABLE = false.B
   def READ_ENABLE   = true.B
   def READ_DISABLE  = false.B
-  def INST_defID    = false.B
-  def INST_INdefID  = true.B
   def SINGLE_ISSUE  = false.B
   def DUAL_ISSUE    = true.B
 
@@ -92,129 +90,6 @@ trait Constants extends CoreParameter {
   def PTEBASE_WID = 9
 }
 
-object FuType {
-  def num     = 5
-  def alu     = "b000".U
-  def lsu     = "b001".U
-  def mdu     = "b010".U
-  def csr     = "b011".U
-  def mou     = "b100".U
-  def bru     = alu
-  def apply() = UInt(log2Up(num).W)
-}
-
-object BTBtype {
-  def B = "b00".U // branch
-  def J = "b01".U // jump
-  def I = "b10".U // indirect
-  def R = "b11".U // return
-
-  def apply() = UInt(2.W)
-}
-
-object ALUOpType {
-  def add  = "b1000000".U
-  def sll  = "b0000001".U
-  def slt  = "b0000010".U
-  def sltu = "b0000011".U
-  def xor  = "b0000100".U
-  def srl  = "b0000101".U
-  def or   = "b0000110".U
-  def and  = "b0000111".U
-  def sub  = "b0001000".U
-  def sra  = "b0001101".U
-
-  def addw = "b1100000".U
-  def subw = "b0101000".U
-  def sllw = "b0100001".U
-  def srlw = "b0100101".U
-  def sraw = "b0101101".U
-
-  def isWordOp(func: UInt) = func(5)
-
-  def jal  = "b1011000".U
-  def jalr = "b1011010".U
-  def beq  = "b0010000".U
-  def bne  = "b0010001".U
-  def blt  = "b0010100".U
-  def bge  = "b0010101".U
-  def bltu = "b0010110".U
-  def bgeu = "b0010111".U
-
-  // for RAS
-  def call = "b1011100".U
-  def ret  = "b1011110".U
-
-  def isAdd(func:          UInt) = func(6)
-  def pcPlus2(func:        UInt) = func(5)
-  def isBru(func:          UInt) = func(4)
-  def isBranch(func:       UInt) = !func(3)
-  def isJump(func:         UInt) = isBru(func) && !isBranch(func)
-  def getBranchType(func:  UInt) = func(2, 1)
-  def isBranchInvert(func: UInt) = func(0)
-}
-
-object LSUOpType { //TODO: refactor LSU fuop
-  def lb  = "b0000000".U
-  def lh  = "b0000001".U
-  def lw  = "b0000010".U
-  def ld  = "b0000011".U
-  def lbu = "b0000100".U
-  def lhu = "b0000101".U
-  def lwu = "b0000110".U
-  def sb  = "b0001000".U
-  def sh  = "b0001001".U
-  def sw  = "b0001010".U
-  def sd  = "b0001011".U
-
-  def lr      = "b0100000".U
-  def sc      = "b0100001".U
-  def amoswap = "b0100010".U
-  def amoadd  = "b1100011".U
-  def amoxor  = "b0100100".U
-  def amoand  = "b0100101".U
-  def amoor   = "b0100110".U
-  def amomin  = "b0110111".U
-  def amomax  = "b0110000".U
-  def amominu = "b0110001".U
-  def amomaxu = "b0110010".U
-
-  def isAdd(func:   UInt) = func(6)
-  def isAtom(func:  UInt): Bool = func(5)
-  def isStore(func: UInt): Bool = func(3)
-  def isLoad(func:  UInt): Bool = !isStore(func) & !isAtom(func)
-  def isLR(func:    UInt): Bool = func === lr
-  def isSC(func:    UInt): Bool = func === sc
-  def isAMO(func:   UInt): Bool = isAtom(func) && !isLR(func) && !isSC(func)
-
-  def needMemRead(func:  UInt): Bool = isLoad(func) || isAMO(func) || isLR(func)
-  def needMemWrite(func: UInt): Bool = isStore(func) || isAMO(func) || isSC(func)
-
-  def atomW = "010".U
-  def atomD = "011".U
-}
-
-object MDUOpType {
-  def mul    = "b0000".U
-  def mulh   = "b0001".U
-  def mulhsu = "b0010".U
-  def mulhu  = "b0011".U
-  def div    = "b0100".U
-  def divu   = "b0101".U
-  def rem    = "b0110".U
-  def remu   = "b0111".U
-
-  def mulw  = "b1000".U
-  def divw  = "b1100".U
-  def divuw = "b1101".U
-  def remw  = "b1110".U
-  def remuw = "b1111".U
-
-  def isDiv(op:     UInt) = op(2)
-  def isDivSign(op: UInt) = isDiv(op) && !op(0)
-  def isW(op:       UInt) = op(3)
-}
-
 trait AXIConst {
   // AXI
   def BURST_FIXED    = 0
@@ -228,3 +103,10 @@ trait AXIConst {
   def RESP_DECERR = 3
 }
 object Const extends Constants with AXIConst
+
+object Instructions extends HasInstrType with CoreParameter {
+  def NOP           = 0x00000013.U
+  val DecodeDefault = List(InstrN, FuType.csr, CSROpType.jmp)
+  def DecodeTable = RVIInstr.table ++ (if (config.hasMExtension) RVMInstr.table else Array.empty) ++
+    Priviledged.table
+}

chisel/playground/src/defines/isa/Instructions.scala

@@ -3,6 +3,165 @@ package cpu.defines
 import chisel3._
 import chisel3.util._
 
+trait HasInstrType {
+  def InstrN  = "b0000".U
+  def InstrI  = "b0100".U
+  def InstrR  = "b0101".U
+  def InstrS  = "b0010".U
+  def InstrB  = "b0001".U
+  def InstrU  = "b0110".U
+  def InstrJ  = "b0111".U
+  def InstrA  = "b1110".U
+  def InstrSA = "b1111".U // Atom Inst: SC
+
+  def isrfWen(instrType: UInt): Bool = instrType(2)
+}
+
+object FuType {
+  def num     = 5
+  def alu     = "b000".U
+  def lsu     = "b001".U
+  def mdu     = "b010".U
+  def csr     = "b011".U
+  def mou     = "b100".U
+  def bru     = alu
+  def apply() = UInt(log2Up(num).W)
+}
+
+// BTB
+object BTBtype {
+  def B = "b00".U // branch
+  def J = "b01".U // jump
+  def I = "b10".U // indirect
+  def R = "b11".U // return
+
+  def apply() = UInt(2.W)
+}
+
+// ALU
+object ALUOpType {
+  def add  = "b1000000".U
+  def sll  = "b0000001".U
+  def slt  = "b0000010".U
+  def sltu = "b0000011".U
+  def xor  = "b0000100".U
+  def srl  = "b0000101".U
+  def or   = "b0000110".U
+  def and  = "b0000111".U
+  def sub  = "b0001000".U
+  def sra  = "b0001101".U
+
+  def addw = "b1100000".U
+  def subw = "b0101000".U
+  def sllw = "b0100001".U
+  def srlw = "b0100101".U
+  def sraw = "b0101101".U
+
+  def isWordOp(func: UInt) = func(5)
+
+  def jal  = "b1011000".U
+  def jalr = "b1011010".U
+  def beq  = "b0010000".U
+  def bne  = "b0010001".U
+  def blt  = "b0010100".U
+  def bge  = "b0010101".U
+  def bltu = "b0010110".U
+  def bgeu = "b0010111".U
+
+  // for RAS
+  def call = "b1011100".U
+  def ret  = "b1011110".U
+
+  def isAdd(func:          UInt) = func(6)
+  def pcPlus2(func:        UInt) = func(5)
+  def isBru(func:          UInt) = func(4)
+  def isBranch(func:       UInt) = !func(3)
+  def isJump(func:         UInt) = isBru(func) && !isBranch(func)
+  def getBranchType(func:  UInt) = func(2, 1)
+  def isBranchInvert(func: UInt) = func(0)
+}
+
+// load store unit
+object LSUOpType { //TODO: refactor LSU fuop
+  def lb  = "b0000000".U
+  def lh  = "b0000001".U
+  def lw  = "b0000010".U
+  def ld  = "b0000011".U
+  def lbu = "b0000100".U
+  def lhu = "b0000101".U
+  def lwu = "b0000110".U
+  def sb  = "b0001000".U
+  def sh  = "b0001001".U
+  def sw  = "b0001010".U
+  def sd  = "b0001011".U
+
+  def lr      = "b0100000".U
+  def sc      = "b0100001".U
+  def amoswap = "b0100010".U
+  def amoadd  = "b1100011".U
+  def amoxor  = "b0100100".U
+  def amoand  = "b0100101".U
+  def amoor   = "b0100110".U
+  def amomin  = "b0110111".U
+  def amomax  = "b0110000".U
+  def amominu = "b0110001".U
+  def amomaxu = "b0110010".U
+
+  def isAdd(func:   UInt) = func(6)
+  def isAtom(func:  UInt): Bool = func(5)
+  def isStore(func: UInt): Bool = func(3)
+  def isLoad(func:  UInt): Bool = !isStore(func) & !isAtom(func)
+  def isLR(func:    UInt): Bool = func === lr
+  def isSC(func:    UInt): Bool = func === sc
+  def isAMO(func:   UInt): Bool = isAtom(func) && !isLR(func) && !isSC(func)
+
+  def needMemRead(func:  UInt): Bool = isLoad(func) || isAMO(func) || isLR(func)
+  def needMemWrite(func: UInt): Bool = isStore(func) || isAMO(func) || isSC(func)
+
+  def atomW = "010".U
+  def atomD = "011".U
+}
+
+// memory order unit
+object MOUOpType {
+  def fence      = "b00".U
+  def fencei     = "b01".U
+  def sfence_vma = "b10".U
+}
+
+// mul div unit
+object MDUOpType {
+  def mul    = "b0000".U
+  def mulh   = "b0001".U
+  def mulhsu = "b0010".U
+  def mulhu  = "b0011".U
+  def div    = "b0100".U
+  def divu   = "b0101".U
+  def rem    = "b0110".U
+  def remu   = "b0111".U
+
+  def mulw  = "b1000".U
+  def divw  = "b1100".U
+  def divuw = "b1101".U
+  def remw  = "b1110".U
+  def remuw = "b1111".U
+
+  def isDiv(op:     UInt) = op(2)
+  def isDivSign(op: UInt) = isDiv(op) && !op(0)
+  def isW(op:       UInt) = op(3)
+}
+
+// csr unit
+object CSROpType {
+  def jmp  = "b000".U
+  def wrt  = "b001".U
+  def set  = "b010".U
+  def clr  = "b011".U
+  def wrti = "b101".U
+  def seti = "b110".U
+  def clri = "b111".U
+}
+
 object Causes {
   val misaligned_fetch         = 0x0
   val fetch_access             = 0x1

chisel/playground/src/defines/isa/Priviledged.scala

@@ -0,0 +1,28 @@
+package cpu.defines
+
+import chisel3._
+import chisel3.util._
+
+object Priviledged extends HasInstrType with CoreParameter {
+  def ECALL      = BitPat("b000000000000_00000_000_00000_1110011")
+  def EBREAK     = BitPat("b000000000001_00000_000_00000_1110011")
+  def MRET       = BitPat("b001100000010_00000_000_00000_1110011")
+  def SRET       = BitPat("b000100000010_00000_000_00000_1110011")
+  def SFANCE_VMA = BitPat("b0001001_?????_?????_000_00000_1110011")
+  def FENCE      = BitPat("b????????????_?????_000_?????_0001111")
+  def WFI        = BitPat("b0001000_00101_00000_000_00000_1110011")
+
+  val table_s = Array(
+    SRET       -> List(InstrI, FuType.csr, CSROpType.jmp),
+    SFANCE_VMA -> List(InstrR, FuType.mou, MOUOpType.sfence_vma)
+  )
+
+  val table = Array(
+    ECALL  -> List(InstrI, FuType.csr, CSROpType.jmp),
+    EBREAK -> List(InstrI, FuType.csr, CSROpType.jmp),
+    MRET   -> List(InstrI, FuType.csr, CSROpType.jmp),
+    FENCE  -> List(InstrS, FuType.mou, MOUOpType.fence), // nop    InstrS -> !wen
+    WFI    -> List(InstrI, FuType.alu, ALUOpType.add) // nop
+    // FENCE          -> List(InstrB, FuType.mou, MOUOpType.fencei)
+  ) ++ (if (config.hasSMode) table_s else Array.empty)
+}

chisel/playground/src/defines/isa/RVI.scala

@@ -3,20 +3,6 @@ package cpu.defines
 import chisel3._
 import chisel3.util._
 
-trait HasInstrType {
-  def InstrN  = "b0000".U
-  def InstrI  = "b0100".U
-  def InstrR  = "b0101".U
-  def InstrS  = "b0010".U
-  def InstrB  = "b0001".U
-  def InstrU  = "b0110".U
-  def InstrJ  = "b0111".U
-  def InstrA  = "b1110".U
-  def InstrSA = "b1111".U // Atom Inst: SC
-
-  def isrfWen(instrType: UInt): Bool = instrType(2)
-}
-
 object RV32I_ALUInstr extends HasInstrType with CoreParameter {
   def ADDI = BitPat("b????????????_?????_000_?????_0010011")
   def SLLI = if (XLEN == 32) BitPat("b0000000?????_?????_001_?????_0010011")

chisel/playground/src/defines/isa/RVM.scala

@@ -30,7 +30,7 @@ object RV32MInstr extends HasInstrType with CoreParameter {
     REM  -> List(InstrR, FuType.mdu, MDUOpType.rem),
     REMU -> List(InstrR, FuType.mdu, MDUOpType.remu)
   )
-  val table = mulTable ++ (if (config.hasMDU) divTable else Array.empty)
+  val table = mulTable ++ (if (config.hasMExtension) divTable else Array.empty)
 }
 
 object RV64MInstr extends HasInstrType with CoreParameter {
@@ -49,7 +49,7 @@ object RV64MInstr extends HasInstrType with CoreParameter {
     REMW  -> List(InstrR, FuType.mdu, MDUOpType.remw),
     REMUW -> List(InstrR, FuType.mdu, MDUOpType.remuw)
   )
-  val table = mulTable ++ (if (config.hasMDU) divTable else Array.empty)
+  val table = mulTable ++ (if (config.hasMExtension) divTable else Array.empty)
 }
 
 object RVMInstr extends CoreParameter {

chisel/playground/src/pipeline/decoder/Decoder.scala

@@ -14,194 +14,12 @@ class Decoder extends Module {
     // outputs
     val out = Output(new InstInfo())
   })
+  
   val inst = io.in.inst
 
-  val table: Array[(BitPat, List[BitPat])] = Array(
+  val instrType :: fuType :: fuOpType :: Nil = // insert Instructions.DecodeDefault when interrupt comes
-    BNE->       List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SNE,   N,M_X,        N,N,N,N,N,N,N,CSR.N,N,N,N,N),
+    Instructions.DecodeDefault.zip(decodeList).map{case (inst, dec) => Mux(hasIntr || io.in.bits.exceptionVec(instrPageFault) || io.out.bits.cf.exceptionVec(instrAccessFault), inst, dec)}
-    BEQ->       List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SEQ,   N,M_X,        N,N,N,N,N,N,N,CSR.N,N,N,N,N),
-    BLT->       List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SLT,   N,M_X,        N,N,N,N,N,N,N,CSR.N,N,N,N,N),
-    BLTU->      List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SLTU,  N,M_X,        N,N,N,N,N,N,N,CSR.N,N,N,N,N),
-    BGE->       List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SGE,   N,M_X,        N,N,N,N,N,N,N,CSR.N,N,N,N,N),
-    BGEU->      List(Y,N,N,Y,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_SB,DW_XPR,aluFn.FN_SGEU,  N,M_X,        N,N,N,N,N,N,N,CSR.N,N,N,N,N),
 
-    JAL->       List(Y,N,N,N,Y,N,N,N,N,N,N,A2_SIZE,A1_PC,  IMM_UJ,DW_XPR,aluFn.FN_ADD,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    JALR->      List(Y,N,N,N,N,Y,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    AUIPC->     List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_PC,  IMM_U, DW_XPR,aluFn.FN_ADD,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-
-    LB->        List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD,   Y,M_XRD,      N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    LH->        List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD,   Y,M_XRD,      N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    LW->        List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD,   Y,M_XRD,      N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    LBU->       List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD,   Y,M_XRD,      N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    LHU->       List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD,   Y,M_XRD,      N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    SB->        List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD,   Y,M_XWR,      N,N,N,N,N,N,N,CSR.N,N,N,N,N),
-    SH->        List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD,   Y,M_XWR,      N,N,N,N,N,N,N,CSR.N,N,N,N,N),
-    SW->        List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_IMM, A1_RS1, IMM_S, DW_XPR,aluFn.FN_ADD,   Y,M_XWR,      N,N,N,N,N,N,N,CSR.N,N,N,N,N),
-
-    LUI->       List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,aluFn.FN_ADD,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    ADDI->      List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_ADD,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    SLTI ->     List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SLT,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    SLTIU->     List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_SLTU,  N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    ANDI->      List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_AND,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    ORI->       List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_OR,    N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    XORI->      List(Y,N,N,N,N,N,N,Y,N,N,N,A2_IMM, A1_RS1, IMM_I, DW_XPR,aluFn.FN_XOR,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    ADD->       List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    SUB->       List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SUB,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    SLT->       List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SLT,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    SLTU->      List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SLTU,  N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    AND->       List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_AND,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    OR->        List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_OR,    N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    XOR->       List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_XOR,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    SLL->       List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SL,    N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    SRL->       List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SR,    N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-    SRA->       List(Y,N,N,N,N,N,Y,Y,N,N,N,A2_RS2, A1_RS1, IMM_X, DW_XPR,aluFn.FN_SRA,   N,M_X,        N,N,N,N,N,N,Y,CSR.N,N,N,N,N),
-
-    FENCE->     List(Y,N,N,N,N,N,N,N,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  aluFn.FN_X,     N,M_X,        N,N,N,N,N,N,N,CSR.N,N,Y,N,N),
-
-    ECALL->     List(Y,N,N,N,N,N,N,X,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  aluFn.FN_X,     N,M_X,        N,N,N,N,N,N,N,CSR.I,N,N,N,N),
-    EBREAK->    List(Y,N,N,N,N,N,N,X,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  aluFn.FN_X,     N,M_X,        N,N,N,N,N,N,N,CSR.I,N,N,N,N),
-    MRET->      List(Y,N,N,N,N,N,N,X,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  aluFn.FN_X,     N,M_X,        N,N,N,N,N,N,N,CSR.I,N,N,N,N),
-    WFI->       List(Y,N,N,N,N,N,N,X,N,N,N,A2_X,   A1_X,   IMM_X, DW_X,  aluFn.FN_X,     N,M_X,        N,N,N,N,N,N,N,CSR.I,N,N,N,N),
-    CSRRW->     List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD,   N,M_X,        N,N,N,N,N,N,Y,CSR.W,N,N,N,N),
-    CSRRS->     List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD,   N,M_X,        N,N,N,N,N,N,Y,CSR.S,N,N,N,N),
-    CSRRC->     List(Y,N,N,N,N,N,N,Y,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,aluFn.FN_ADD,   N,M_X,        N,N,N,N,N,N,Y,CSR.C,N,N,N,N),
-    CSRRWI->    List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD,   N,M_X,        N,N,N,N,N,N,Y,CSR.W,N,N,N,N),
-    CSRRSI->    List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD,   N,M_X,        N,N,N,N,N,N,Y,CSR.S,N,N,N,N),
-    CSRRCI->    List(Y,N,N,N,N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,aluFn.FN_ADD,   N,M_X,        N,N,N,N,N,N,Y,CSR.C,N,N,N,N))
-
-
-  // val signals: List[UInt] = ListLookup(
-  //   //@formatter:off
-  //   inst,
-  //   List(INST_INVALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
-  //   Array( /* inst_valid | reg1_ren | reg2_ren | fusel | op | reg_wen | reg_waddr | imm_type | dual_issue */
-  //     // NOP
-  //     NOP -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
-  //     // 位操作
-  //     OR  -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_OR,  WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
-  //     AND -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_AND, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
-  //     XOR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_XOR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
-  //     NOR -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_NOR, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
-  //     // 移位
-  //     SLLV -> List(INST_VALID, READ_ENABLE,  READ_ENABLE, FU_ALU, EXE_SLL, WRITE_ENABLE, WRA_T1, IMM_N,   DUAL_ISSUE),
-  //     SRLV -> List(INST_VALID, READ_ENABLE,  READ_ENABLE, FU_ALU, EXE_SRL, WRITE_ENABLE, WRA_T1, IMM_N,   DUAL_ISSUE),
-  //     SRAV -> List(INST_VALID, READ_ENABLE,  READ_ENABLE, FU_ALU, EXE_SRA, WRITE_ENABLE, WRA_T1, IMM_N,   DUAL_ISSUE),
-  //     SLL  -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SLL, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE),
-  //     SRL  -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SRL, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE),
-  //     SRA  -> List(INST_VALID, READ_DISABLE, READ_ENABLE, FU_ALU, EXE_SRA, WRITE_ENABLE, WRA_T1, IMM_SHT, DUAL_ISSUE),
-  //     // 立即数
-  //     ORI  -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_OR,  WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE),
-  //     ANDI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_AND, WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE),
-  //     XORI -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_XOR, WRITE_ENABLE, WRA_T2, IMM_LZE, DUAL_ISSUE),
-  //     LUI  -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_OR,  WRITE_ENABLE, WRA_T2, IMM_HZE, DUAL_ISSUE),
-
-  //     // Move
-  //     MOVN -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_MOVN, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
-  //     MOVZ -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_MOVZ, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
-
-  //     // HI，LO的Move指令
-  //     MFHI -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_MFHILO, EXE_MFHI, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
-  //     MFLO -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_MFHILO, EXE_MFLO, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
-  //     MTHI -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_MTHILO, EXE_MTHI, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
-  //     MTLO -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_MTHILO, EXE_MTLO, WRITE_DISABLE, WRA_X, IMM_N, DUAL_ISSUE),
-
-  //     // C0的Move指令
-  //     MFC0 -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_MFC0, WRITE_ENABLE,  WRA_T2, IMM_N, DUAL_ISSUE),
-  //     MTC0 -> List(INST_VALID, READ_DISABLE, READ_ENABLE,  FU_ALU, EXE_MTC0, WRITE_DISABLE, WRA_X,  IMM_N, SINGLE_ISSUE),
-
-  //     // 比较指令
-  //     SLT  -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SLT,  WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
-  //     SLTU -> List(INST_VALID, READ_ENABLE, READ_ENABLE, FU_ALU, EXE_SLTU, WRITE_ENABLE, WRA_T1, IMM_N, DUAL_ISSUE),
-  //     // 立即数
-  //     SLTI  -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_SLT,  WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE),
-  //     SLTIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_SLTU, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE),
-
-  //     // Trap
-  //     TEQ   -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_EX, EXE_TEQ,  WRITE_DISABLE, WRA_X, IMM_N,   DUAL_ISSUE),
-  //     TEQI  -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TEQ,  WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
-  //     TGE   -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_EX, EXE_TGE,  WRITE_DISABLE, WRA_X, IMM_N,   DUAL_ISSUE),
-  //     TGEI  -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TGE,  WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
-  //     TGEIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TGEU, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
-  //     TGEU  -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_EX, EXE_TGEU, WRITE_DISABLE, WRA_X, IMM_N,   DUAL_ISSUE),
-  //     TLT   -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_EX, EXE_TLT,  WRITE_DISABLE, WRA_X, IMM_N,   DUAL_ISSUE),
-  //     TLTI  -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TLT,  WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
-  //     TLTU  -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_EX, EXE_TLTU, WRITE_DISABLE, WRA_X, IMM_N,   DUAL_ISSUE),
-  //     TLTIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TLTU, WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
-  //     TNE   -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_EX, EXE_TNE,  WRITE_DISABLE, WRA_X, IMM_N,   DUAL_ISSUE),
-  //     TNEI  -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_EX, EXE_TNE,  WRITE_DISABLE, WRA_X, IMM_LSE, DUAL_ISSUE),
-
-  //     // 算术指令 
-  //     ADD   -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_ALU, EXE_ADD,   WRITE_ENABLE,  WRA_T1, IMM_N, DUAL_ISSUE),
-  //     ADDU  -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_ALU, EXE_ADDU,  WRITE_ENABLE,  WRA_T1, IMM_N, DUAL_ISSUE),
-  //     SUB   -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_ALU, EXE_SUB,   WRITE_ENABLE,  WRA_T1, IMM_N, DUAL_ISSUE),
-  //     SUBU  -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_ALU, EXE_SUBU,  WRITE_ENABLE,  WRA_T1, IMM_N, DUAL_ISSUE),
-  //     MUL   -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_MUL, EXE_MUL,   WRITE_ENABLE,  WRA_T1, IMM_N, DUAL_ISSUE),
-  //     MULT  -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_MUL, EXE_MULT,  WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     MULTU -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_MUL, EXE_MULTU, WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     MADD  -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_MUL, EXE_MADD,  WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     MADDU -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_MUL, EXE_MADDU, WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     MSUB  -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_MUL, EXE_MSUB,  WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     MSUBU -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_MUL, EXE_MSUBU, WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     DIV   -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_DIV, EXE_DIV,   WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     DIVU  -> List(INST_VALID, READ_ENABLE, READ_ENABLE,  FU_DIV, EXE_DIVU,  WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     CLO   -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CLO,   WRITE_ENABLE,  WRA_T1, IMM_N, DUAL_ISSUE),
-  //     CLZ   -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CLZ,   WRITE_ENABLE,  WRA_T1, IMM_N, DUAL_ISSUE),
-  //     // 立即数
-  //     ADDI  -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_ADD,  WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE),
-  //     ADDIU -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_ADDU, WRITE_ENABLE, WRA_T2, IMM_LSE, DUAL_ISSUE),
-  //     // 跳转指令
-  //     J      -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_BR, EXE_J,      WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     JAL    -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_BR, EXE_JAL,    WRITE_ENABLE,  WRA_T3, IMM_N, DUAL_ISSUE),
-  //     JR     -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_BR, EXE_JR,     WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     JALR   -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_BR, EXE_JALR,   WRITE_ENABLE,  WRA_T1, IMM_N, DUAL_ISSUE),
-  //     BEQ    -> List(INST_VALID, READ_ENABLE,  READ_ENABLE,  FU_BR, EXE_BEQ,    WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     BNE    -> List(INST_VALID, READ_ENABLE,  READ_ENABLE,  FU_BR, EXE_BNE,    WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     BGTZ   -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_BR, EXE_BGTZ,   WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     BLEZ   -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_BR, EXE_BLEZ,   WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     BGEZ   -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_BR, EXE_BGEZ,   WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     BGEZAL -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_BR, EXE_BGEZAL, WRITE_ENABLE,  WRA_T3, IMM_N, DUAL_ISSUE),
-  //     BLTZ   -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_BR, EXE_BLTZ,   WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     BLTZAL -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_BR, EXE_BLTZAL, WRITE_ENABLE,  WRA_T3, IMM_N, DUAL_ISSUE),
-
-  //     // TLB
-  //     TLBP  -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBP,  WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
-  //     TLBR  -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBR,  WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
-  //     TLBWI -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBWI, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
-  //     TLBWR -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_TLBWR, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
-
-  //     // 例外指令
-  //     SYSCALL -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX,  EXE_SYSCALL, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
-  //     BREAK   -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX,  EXE_BREAK,   WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
-  //     ERET    -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX,  EXE_ERET,    WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
-  //     WAIT    -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP,     WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
-
-  //     // 访存指令
-  //     LB    -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_MEM, EXE_LB,  WRITE_ENABLE,  WRA_T2, IMM_N, DUAL_ISSUE),
-  //     LBU   -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_MEM, EXE_LBU, WRITE_ENABLE,  WRA_T2, IMM_N, DUAL_ISSUE),
-  //     LH    -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_MEM, EXE_LH,  WRITE_ENABLE,  WRA_T2, IMM_N, DUAL_ISSUE),
-  //     LHU   -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_MEM, EXE_LHU, WRITE_ENABLE,  WRA_T2, IMM_N, DUAL_ISSUE),
-  //     LW    -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_MEM, EXE_LW,  WRITE_ENABLE,  WRA_T2, IMM_N, DUAL_ISSUE),
-  //     SB    -> List(INST_VALID, READ_ENABLE,  READ_ENABLE,  FU_MEM, EXE_SB,  WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     SH    -> List(INST_VALID, READ_ENABLE,  READ_ENABLE,  FU_MEM, EXE_SH,  WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     SW    -> List(INST_VALID, READ_ENABLE,  READ_ENABLE,  FU_MEM, EXE_SW,  WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     LWL   -> List(INST_VALID, READ_ENABLE,  READ_ENABLE,  FU_MEM, EXE_LWL, WRITE_ENABLE,  WRA_T2, IMM_N, DUAL_ISSUE),
-  //     LWR   -> List(INST_VALID, READ_ENABLE,  READ_ENABLE,  FU_MEM, EXE_LWR, WRITE_ENABLE,  WRA_T2, IMM_N, DUAL_ISSUE),
-  //     SWL   -> List(INST_VALID, READ_ENABLE,  READ_ENABLE,  FU_MEM, EXE_SWL, WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     SWR   -> List(INST_VALID, READ_ENABLE,  READ_ENABLE,  FU_MEM, EXE_SWR, WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-      
-  //     LL    -> List(INST_VALID, READ_ENABLE,  READ_DISABLE, FU_MEM, EXE_LL,  WRITE_ENABLE,  WRA_T2, IMM_N, DUAL_ISSUE),
-  //     SC    -> List(INST_VALID, READ_ENABLE,  READ_ENABLE,  FU_MEM, EXE_SC,  WRITE_ENABLE,  WRA_T2, IMM_N, DUAL_ISSUE),
-      
-  //     SYNC  -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_EX,  EXE_NOP, WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-  //     PREF  -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_ENABLE,  WRA_X,  IMM_N, DUAL_ISSUE),
-  //     PREFX -> List(INST_VALID, READ_DISABLE, READ_DISABLE, FU_ALU, EXE_NOP, WRITE_DISABLE, WRA_X,  IMM_N, DUAL_ISSUE),
-
-  //     // Cache
-  //     CACHE -> List(INST_VALID, READ_ENABLE, READ_DISABLE, FU_ALU, EXE_CACHE, WRITE_DISABLE, WRA_X, IMM_N, SINGLE_ISSUE),
-  //   ),
-  //   // @formatter:on
-  // )
-  val inst_valid :: reg1_ren :: reg2_ren :: fusel :: op :: reg_wen :: reg_waddr_type :: imm_type :: dual_issue :: Nil =
-    signals
 
   val rt    = inst(20, 16)
   val rd    = inst(15, 11)