refactor: 调整变量名，删除fuNum

chisel/playground/src/Core.scala

@@ -80,7 +80,7 @@ class Core(implicit val config: CpuConfig) extends Module {
   decoderUnit.instFifo.info.empty        := instFifo.empty
   decoderUnit.instFifo.info.almost_empty := instFifo.almost_empty
   decoderUnit.regfile <> regfile.read
-  for (i <- 0 until (config.fuNum)) {
+  for (i <- 0 until (config.commitNum)) {
     decoderUnit.forward(i).exe      := executeUnit.decoderUnit.forward(i).exe
     decoderUnit.forward(i).mem_wreg := executeUnit.decoderUnit.forward(i).exe_mem_wreg
     decoderUnit.forward(i).mem      := memoryUnit.decoderUnit(i)

chisel/playground/src/CpuConfig.scala

@@ -1,6 +1,7 @@
 package cpu
 
 import chisel3.util._
+import cpu.defines.Const._
 
 case class CpuConfig(
   val build: Boolean = false, // 是否为build模式
@@ -13,9 +14,8 @@ case class CpuConfig(
   val hasUMode: Boolean = true, // 是否有U模式
   // 模块配置
   val hasCommitBuffer: Boolean = true, // 是否有提交缓存
-  val decoderNum:      Int     = 2, // 同时访问寄存器的指令数
+  val decoderNum:      Int     = 2, // 译码级最大解码的指令数，也是同时访问寄存器的指令数
-  val commitNum:       Int     = 2, // 同时提交的指令数
+  val commitNum:       Int     = 2, // 同时提交的指令数, 也是最大发射的指令数
-  val fuNum:           Int     = 2, // 功能单元数
   val instFetchNum:    Int     = 2, // iCache取到的指令数量，目前为2和4时验证正确
   val instFifoDepth:   Int     = 8, // 指令缓存深度
   val mulClockNum:     Int     = 2, // 乘法器的时钟周期数
@@ -45,7 +45,7 @@ case class CacheConfig(
   require(isPow2(nbank))
   require(isPow2(bytesPerBank))
   require(
-    tagWidth + indexWidth + bankIndexWidth + bankOffsetWidth == 32,
+    tagWidth + indexWidth + bankIndexWidth + bankOffsetWidth == PADDR_WID,
     "basic request calculation"
   )
 }

chisel/playground/src/defines/Bundles.scala

@@ -77,7 +77,7 @@ class ExecuteFuCtrl extends Bundle {
 }
 
 class ExecuteCtrl(implicit val config: CpuConfig) extends Bundle {
-  val inst     = Output(Vec(config.fuNum, new MemRead()))
+  val inst     = Output(Vec(config.commitNum, new MemRead()))
   val fu_stall = Output(Bool())
   val flush    = Output(Bool())
 

chisel/playground/src/pipeline/decoder/DecoderUnit.scala

@@ -42,7 +42,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
     // 输入
     val instFifo = new InstFifoDecoderUnit()
     val regfile  = Vec(config.decoderNum, new Src12Read())
-    val forward  = Input(Vec(config.fuNum, new DataForwardToDecoderUnit()))
+    val forward  = Input(Vec(config.commitNum, new DataForwardToDecoderUnit()))
     val csr      = Input(new execute.CsrDecoderUnit())
     // 输出
     val fetchUnit = new Bundle {

chisel/playground/src/pipeline/decoder/ForwardCtrl.scala

@@ -10,7 +10,7 @@ import cpu.CpuConfig
 class ForwardCtrl(implicit val config: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val in = Input(new Bundle {
-      val forward = Vec(config.fuNum, new DataForwardToDecoderUnit())
+      val forward = Vec(config.commitNum, new DataForwardToDecoderUnit())
       val regfile = Vec(config.decoderNum, new Src12Read())
     })
     val out = Output(new Bundle {
@@ -28,7 +28,7 @@ class ForwardCtrl(implicit val config: CpuConfig) extends Module {
 
   // mem优先度中
   for (i <- 0 until (config.decoderNum)) {
-    for (j <- 0 until (config.fuNum)) {
+    for (j <- 0 until (config.commitNum)) {
       when(
         io.in.forward(j).mem.wen &&
           io.in.forward(j).mem.waddr === io.in.regfile(i).src1.raddr
@@ -46,7 +46,7 @@ class ForwardCtrl(implicit val config: CpuConfig) extends Module {
 
   // exe优先度高
   for (i <- 0 until (config.decoderNum)) {
-    for (j <- 0 until (config.fuNum)) {
+    for (j <- 0 until (config.commitNum)) {
       when(
         io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg &&
           io.in.forward(j).exe.waddr === io.in.regfile(i).src1.raddr

chisel/playground/src/pipeline/decoder/Issue.scala

@@ -16,7 +16,7 @@ class Issue(implicit val config: CpuConfig) extends Module {
       val almost_empty = Bool()
     })
     val decodeInst = Input(Vec(config.decoderNum, new InstInfo()))
-    val execute    = Input(Vec(config.fuNum, new MemRead()))
+    val execute    = Input(Vec(config.commitNum, new MemRead()))
     // 输出
     val inst1 = Output(new Bundle {
       val allow_to_go = Bool()

chisel/playground/src/pipeline/decoder/JumpCtrl.scala

@@ -13,7 +13,7 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module {
       val pc       = UInt(PC_WID.W)
       val info     = new InstInfo()
       val src_info = new SrcInfo()
-      val forward  = Vec(config.fuNum, new DataForwardToDecoderUnit())
+      val forward  = Vec(config.commitNum, new DataForwardToDecoderUnit())
     })
     val out = Output(new Bundle {
       val jump_inst     = Bool()

chisel/playground/src/pipeline/execute/ExecuteUnit.scala

@@ -22,7 +22,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
     val decoderUnit = new Bundle {
       val forward = Output(
         Vec(
-          config.fuNum,
+          config.commitNum,
           new Bundle {
             val exe          = new RegWrite()
             val exe_mem_wreg = Bool()

chisel/playground/src/pipeline/execute/Fu.scala

@@ -48,7 +48,7 @@ class Fu(implicit val config: CpuConfig) extends Module {
   io.branch.flush  := branchCtrl_flush
   io.branch.target := branchCtrl.out.target
 
-  for (i <- 0 until (config.fuNum)) {
+  for (i <- 0 until (config.commitNum)) {
     alu(i).io.info     := Mux(io.inst(i).info.fusel === FuType.alu, io.inst(i).info, 0.U.asTypeOf(new InstInfo()))
     alu(i).io.src_info := Mux(io.inst(i).info.fusel === FuType.alu, io.inst(i).src_info, 0.U.asTypeOf(new SrcInfo()))
   }

chisel/playground/src/pipeline/memory/MemoryUnit.scala

@@ -17,7 +17,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
       val flush  = Bool()
       val target = UInt(PC_WID.W)
     })
-    val decoderUnit    = Output(Vec(config.fuNum, new RegWrite()))
+    val decoderUnit    = Output(Vec(config.commitNum, new RegWrite()))
     val csr            = Flipped(new CsrMemoryUnit())
     val writeBackStage = Output(new MemoryUnitWriteBackUnit())
     val dataMemory     = new DataMemoryAccess_DataMemory()