From a94958d7c9afbcf1f1d4c0f3f746f04b8de4d2a3 Mon Sep 17 00:00:00 2001 From: Liphen Date: Sun, 24 Dec 2023 13:17:55 +0800 Subject: [PATCH] =?UTF-8?q?refactor:=20=E8=B0=83=E6=95=B4=E5=8F=98?= =?UTF-8?q?=E9=87=8F=E5=90=8D=EF=BC=8C=E5=88=A0=E9=99=A4fuNum?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/Core.scala | 2 +- chisel/playground/src/CpuConfig.scala | 8 ++++---- chisel/playground/src/defines/Bundles.scala | 2 +- chisel/playground/src/pipeline/decoder/DecoderUnit.scala | 2 +- chisel/playground/src/pipeline/decoder/ForwardCtrl.scala | 6 +++--- chisel/playground/src/pipeline/decoder/Issue.scala | 2 +- chisel/playground/src/pipeline/decoder/JumpCtrl.scala | 2 +- chisel/playground/src/pipeline/execute/ExecuteUnit.scala | 2 +- chisel/playground/src/pipeline/execute/Fu.scala | 2 +- chisel/playground/src/pipeline/memory/MemoryUnit.scala | 2 +- 10 files changed, 15 insertions(+), 15 deletions(-) diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala index 70e713f..51e07aa 100644 --- a/chisel/playground/src/Core.scala +++ b/chisel/playground/src/Core.scala @@ -80,7 +80,7 @@ class Core(implicit val config: CpuConfig) extends Module { decoderUnit.instFifo.info.empty := instFifo.empty decoderUnit.instFifo.info.almost_empty := instFifo.almost_empty decoderUnit.regfile <> regfile.read - for (i <- 0 until (config.fuNum)) { + for (i <- 0 until (config.commitNum)) { decoderUnit.forward(i).exe := executeUnit.decoderUnit.forward(i).exe decoderUnit.forward(i).mem_wreg := executeUnit.decoderUnit.forward(i).exe_mem_wreg decoderUnit.forward(i).mem := memoryUnit.decoderUnit(i) diff --git a/chisel/playground/src/CpuConfig.scala b/chisel/playground/src/CpuConfig.scala index 6e63e66..454497c 100644 --- a/chisel/playground/src/CpuConfig.scala +++ b/chisel/playground/src/CpuConfig.scala @@ -1,6 +1,7 @@ package cpu import chisel3.util._ +import cpu.defines.Const._ case class CpuConfig( val build: Boolean = false, // 是否为build模式 @@ -13,9 +14,8 @@ case class CpuConfig( val hasUMode: Boolean = true, // 是否有U模式 // 模块配置 val hasCommitBuffer: Boolean = true, // 是否有提交缓存 - val decoderNum: Int = 2, // 同时访问寄存器的指令数 - val commitNum: Int = 2, // 同时提交的指令数 - val fuNum: Int = 2, // 功能单元数 + val decoderNum: Int = 2, // 译码级最大解码的指令数，也是同时访问寄存器的指令数 + val commitNum: Int = 2, // 同时提交的指令数, 也是最大发射的指令数 val instFetchNum: Int = 2, // iCache取到的指令数量，目前为2和4时验证正确 val instFifoDepth: Int = 8, // 指令缓存深度 val mulClockNum: Int = 2, // 乘法器的时钟周期数 @@ -45,7 +45,7 @@ case class CacheConfig( require(isPow2(nbank)) require(isPow2(bytesPerBank)) require( - tagWidth + indexWidth + bankIndexWidth + bankOffsetWidth == 32, + tagWidth + indexWidth + bankIndexWidth + bankOffsetWidth == PADDR_WID, "basic request calculation" ) } diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala index ba7e70a..cc5aee9 100644 --- a/chisel/playground/src/defines/Bundles.scala +++ b/chisel/playground/src/defines/Bundles.scala @@ -77,7 +77,7 @@ class ExecuteFuCtrl extends Bundle { } class ExecuteCtrl(implicit val config: CpuConfig) extends Bundle { - val inst = Output(Vec(config.fuNum, new MemRead())) + val inst = Output(Vec(config.commitNum, new MemRead())) val fu_stall = Output(Bool()) val flush = Output(Bool()) diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala index 87f9b46..6513b0e 100644 --- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala +++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala @@ -42,7 +42,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti // 输入 val instFifo = new InstFifoDecoderUnit() val regfile = Vec(config.decoderNum, new Src12Read()) - val forward = Input(Vec(config.fuNum, new DataForwardToDecoderUnit())) + val forward = Input(Vec(config.commitNum, new DataForwardToDecoderUnit())) val csr = Input(new execute.CsrDecoderUnit()) // 输出 val fetchUnit = new Bundle { diff --git a/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala b/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala index 1916f94..239e1e3 100644 --- a/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala +++ b/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala @@ -10,7 +10,7 @@ import cpu.CpuConfig class ForwardCtrl(implicit val config: CpuConfig) extends Module { val io = IO(new Bundle { val in = Input(new Bundle { - val forward = Vec(config.fuNum, new DataForwardToDecoderUnit()) + val forward = Vec(config.commitNum, new DataForwardToDecoderUnit()) val regfile = Vec(config.decoderNum, new Src12Read()) }) val out = Output(new Bundle { @@ -28,7 +28,7 @@ class ForwardCtrl(implicit val config: CpuConfig) extends Module { // mem优先度中 for (i <- 0 until (config.decoderNum)) { - for (j <- 0 until (config.fuNum)) { + for (j <- 0 until (config.commitNum)) { when( io.in.forward(j).mem.wen && io.in.forward(j).mem.waddr === io.in.regfile(i).src1.raddr @@ -46,7 +46,7 @@ class ForwardCtrl(implicit val config: CpuConfig) extends Module { // exe优先度高 for (i <- 0 until (config.decoderNum)) { - for (j <- 0 until (config.fuNum)) { + for (j <- 0 until (config.commitNum)) { when( io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg && io.in.forward(j).exe.waddr === io.in.regfile(i).src1.raddr diff --git a/chisel/playground/src/pipeline/decoder/Issue.scala b/chisel/playground/src/pipeline/decoder/Issue.scala index ced94a7..d00df91 100644 --- a/chisel/playground/src/pipeline/decoder/Issue.scala +++ b/chisel/playground/src/pipeline/decoder/Issue.scala @@ -16,7 +16,7 @@ class Issue(implicit val config: CpuConfig) extends Module { val almost_empty = Bool() }) val decodeInst = Input(Vec(config.decoderNum, new InstInfo())) - val execute = Input(Vec(config.fuNum, new MemRead())) + val execute = Input(Vec(config.commitNum, new MemRead())) // 输出 val inst1 = Output(new Bundle { val allow_to_go = Bool() diff --git a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala index e760163..5f378c4 100644 --- a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala +++ b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala @@ -13,7 +13,7 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module { val pc = UInt(PC_WID.W) val info = new InstInfo() val src_info = new SrcInfo() - val forward = Vec(config.fuNum, new DataForwardToDecoderUnit()) + val forward = Vec(config.commitNum, new DataForwardToDecoderUnit()) }) val out = Output(new Bundle { val jump_inst = Bool() diff --git a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala index 041d7ad..17cd618 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteUnit.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteUnit.scala @@ -22,7 +22,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module { val decoderUnit = new Bundle { val forward = Output( Vec( - config.fuNum, + config.commitNum, new Bundle { val exe = new RegWrite() val exe_mem_wreg = Bool() diff --git a/chisel/playground/src/pipeline/execute/Fu.scala b/chisel/playground/src/pipeline/execute/Fu.scala index aeb2d29..829b2ba 100644 --- a/chisel/playground/src/pipeline/execute/Fu.scala +++ b/chisel/playground/src/pipeline/execute/Fu.scala @@ -48,7 +48,7 @@ class Fu(implicit val config: CpuConfig) extends Module { io.branch.flush := branchCtrl_flush io.branch.target := branchCtrl.out.target - for (i <- 0 until (config.fuNum)) { + for (i <- 0 until (config.commitNum)) { alu(i).io.info := Mux(io.inst(i).info.fusel === FuType.alu, io.inst(i).info, 0.U.asTypeOf(new InstInfo())) alu(i).io.src_info := Mux(io.inst(i).info.fusel === FuType.alu, io.inst(i).src_info, 0.U.asTypeOf(new SrcInfo())) } diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala index 4fb5ea8..b91f327 100644 --- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala +++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala @@ -17,7 +17,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module { val flush = Bool() val target = UInt(PC_WID.W) }) - val decoderUnit = Output(Vec(config.fuNum, new RegWrite())) + val decoderUnit = Output(Vec(config.commitNum, new RegWrite())) val csr = Flipped(new CsrMemoryUnit()) val writeBackStage = Output(new MemoryUnitWriteBackUnit()) val dataMemory = new DataMemoryAccess_DataMemory()