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refactor(csr): mem改为单输入

This commit is contained in:
Liphen 2023-12-21 15:38:02 +08:00
parent f13b9f009f
commit 9d597adfa1
2 changed files with 44 additions and 40 deletions
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24
chisel/playground/src/pipeline/execute/Csr.scala
View File

@ -9,14 +9,10 @@ import chisel3.util.experimental.BoringUtils
class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle { class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
val in = Input(new Bundle { val in = Input(new Bundle {
val inst = Vec(
config.fuNum,
new Bundle {
val pc = UInt(PC_WID.W) val pc = UInt(PC_WID.W)
val ex = new ExceptionInfo() val ex = new ExceptionInfo()
val info = new InstInfo() val info = new InstInfo()
}
)
val set_lr = Bool() val set_lr = Bool()
val set_lr_val = Bool() val set_lr_val = Bool()
val set_lr_addr = UInt(DATA_ADDR_WID.W) val set_lr_addr = UInt(DATA_ADDR_WID.W)
@ -69,12 +65,12 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
val misa_init = Wire(new Misa()) val misa_init = Wire(new Misa())
misa_init := 0.U.asTypeOf(new Misa()) misa_init := 0.U.asTypeOf(new Misa())
misa_init.mxl := 2.U misa_init.mxl := 2.U
def getMisaExt(ext: Char): UInt = {1.U << (ext.toInt - 'a'.toInt)} def getMisaExt(ext: Char): UInt = { 1.U << (ext.toInt - 'a'.toInt) }
var extensions = List('i') var extensions = List('i')
if(config.hasMExtension){ extensions = extensions :+ 'm'} if (config.hasMExtension) { extensions = extensions :+ 'm' }
if(config.hasAExtension){ extensions = extensions :+ 'a'} if (config.hasAExtension) { extensions = extensions :+ 'a' }
if(config.hasSMode){ extensions = extensions :+ 's'} if (config.hasSMode) { extensions = extensions :+ 's' }
if(config.hasUMode){ extensions = extensions :+ 'u'} if (config.hasUMode) { extensions = extensions :+ 'u' }
misa_init.extensions := extensions.foldLeft(0.U)((sum, i) => sum | getMisaExt(i)) misa_init.extensions := extensions.foldLeft(0.U)((sum, i) => sum | getMisaExt(i))
val misa = RegInit(UInt(XLEN.W), misa_init.asUInt) // ISA寄存器 val misa = RegInit(UInt(XLEN.W), misa_init.asUInt) // ISA寄存器
val mie = RegInit(0.U(XLEN.W)) // 中断使能寄存器 val mie = RegInit(0.U(XLEN.W)) // 中断使能寄存器
@ -233,11 +229,9 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
io.decoderUnit.interrupt := mie(11, 0) & mip_has_interrupt.asUInt & interrupt_enable.asUInt io.decoderUnit.interrupt := mie(11, 0) & mip_has_interrupt.asUInt & interrupt_enable.asUInt
// 优先使用inst0的信息 // 优先使用inst0的信息
val exc_sel = val mem_pc = io.memoryUnit.in.pc
(HasExcInt(io.memoryUnit.in.inst(0).ex)) || !(HasExcInt(io.memoryUnit.in.inst(1).ex)) val mem_ex = io.memoryUnit.in.ex
val mem_pc = Mux(exc_sel, io.memoryUnit.in.inst(0).pc, io.memoryUnit.in.inst(1).pc) val mem_inst_info = io.memoryUnit.in.info
val mem_ex = Mux(exc_sel, io.memoryUnit.in.inst(0).ex, io.memoryUnit.in.inst(1).ex)
val mem_inst_info = Mux(exc_sel, io.memoryUnit.in.inst(0).info, io.memoryUnit.in.inst(1).info)
val mem_inst = mem_inst_info.inst val mem_inst = mem_inst_info.inst
val mem_valid = mem_inst_info.valid val mem_valid = mem_inst_info.valid
val mem_addr = mem_inst(31, 20) val mem_addr = mem_inst(31, 20)

34
chisel/playground/src/pipeline/memory/MemoryUnit.scala
View File

@ -92,19 +92,29 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
io.writeBackStage.inst1.commit := io.memoryStage.inst1.info.valid && io.writeBackStage.inst1.commit := io.memoryStage.inst1.info.valid &&
!(HasExcInt(io.writeBackStage.inst0.ex)) !(HasExcInt(io.writeBackStage.inst0.ex))
io.csr.in.inst(0).pc := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst0.pc, 0.U) val csr_sel =
io.csr.in.inst(0).ex := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst0.ex, 0.U.asTypeOf(new ExceptionInfo())) HasExcInt(io.writeBackStage.inst0.ex) || !HasExcInt(io.writeBackStage.inst1.ex)
io.csr.in.inst(0).info := Mux(
io.ctrl.allow_to_go, io.csr.in.pc := MuxCase(
io.writeBackStage.inst0.info, 0.U,
0.U.asTypeOf(new InstInfo()) Seq(
(io.ctrl.allow_to_go && csr_sel) -> io.writeBackStage.inst0.pc,
(io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst1.pc
)
)
io.csr.in.ex := MuxCase(
0.U.asTypeOf(new ExceptionInfo()),
Seq(
(io.ctrl.allow_to_go && csr_sel) -> io.writeBackStage.inst0.ex,
(io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst1.ex
)
)
io.csr.in.info := MuxCase(
0.U.asTypeOf(new InstInfo()),
Seq(
(io.ctrl.allow_to_go && csr_sel) -> io.writeBackStage.inst0.info,
(io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst1.info
) )
io.csr.in.inst(1).pc := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst1.pc, 0.U)
io.csr.in.inst(1).ex := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst1.ex, 0.U.asTypeOf(new ExceptionInfo()))
io.csr.in.inst(1).info := Mux(
io.ctrl.allow_to_go,
io.writeBackStage.inst1.info,
0.U.asTypeOf(new InstInfo())
) )
io.csr.in.set_lr := dataMemoryAccess.memoryUnit.out.set_lr && io.ctrl.allow_to_go io.csr.in.set_lr := dataMemoryAccess.memoryUnit.out.set_lr && io.ctrl.allow_to_go