From 9d597adfa14afdab33fd90c1ab090e25710dc0f8 Mon Sep 17 00:00:00 2001 From: Liphen Date: Thu, 21 Dec 2023 15:38:02 +0800 Subject: [PATCH] =?UTF-8?q?refactor(csr):=20mem=E6=94=B9=E4=B8=BA=E5=8D=95?= =?UTF-8?q?=E8=BE=93=E5=85=A5?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../playground/src/pipeline/execute/Csr.scala | 50 ++++++++----------- .../src/pipeline/memory/MemoryUnit.scala | 34 ++++++++----- 2 files changed, 44 insertions(+), 40 deletions(-) diff --git a/chisel/playground/src/pipeline/execute/Csr.scala b/chisel/playground/src/pipeline/execute/Csr.scala index a1fd7da..3c19869 100644 --- a/chisel/playground/src/pipeline/execute/Csr.scala +++ b/chisel/playground/src/pipeline/execute/Csr.scala @@ -9,14 +9,10 @@ import chisel3.util.experimental.BoringUtils class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle { val in = Input(new Bundle { - val inst = Vec( - config.fuNum, - new Bundle { - val pc = UInt(PC_WID.W) - val ex = new ExceptionInfo() - val info = new InstInfo() - } - ) + val pc = UInt(PC_WID.W) + val ex = new ExceptionInfo() + val info = new InstInfo() + val set_lr = Bool() val set_lr_val = Bool() val set_lr_addr = UInt(DATA_ADDR_WID.W) @@ -50,7 +46,7 @@ class CsrDecoderUnit extends Bundle { class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst { val io = IO(new Bundle { - val ext_int = Input(new ExtInterrupt()) + val ext_int = Input(new ExtInterrupt()) val decoderUnit = new CsrDecoderUnit() val executeUnit = new CsrExecuteUnit() val memoryUnit = new CsrMemoryUnit() @@ -67,14 +63,14 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst { mstatus_init.uxl := 2.U val mstatus = RegInit(UInt(XLEN.W), mstatus_init.asUInt) // 状态寄存器 val misa_init = Wire(new Misa()) - misa_init := 0.U.asTypeOf(new Misa()) - misa_init.mxl := 2.U - def getMisaExt(ext: Char): UInt = {1.U << (ext.toInt - 'a'.toInt)} + misa_init := 0.U.asTypeOf(new Misa()) + misa_init.mxl := 2.U + def getMisaExt(ext: Char): UInt = { 1.U << (ext.toInt - 'a'.toInt) } var extensions = List('i') - if(config.hasMExtension){ extensions = extensions :+ 'm'} - if(config.hasAExtension){ extensions = extensions :+ 'a'} - if(config.hasSMode){ extensions = extensions :+ 's'} - if(config.hasUMode){ extensions = extensions :+ 'u'} + if (config.hasMExtension) { extensions = extensions :+ 'm' } + if (config.hasAExtension) { extensions = extensions :+ 'a' } + if (config.hasSMode) { extensions = extensions :+ 's' } + if (config.hasUMode) { extensions = extensions :+ 'u' } misa_init.extensions := extensions.foldLeft(0.U)((sum, i) => sum | getMisaExt(i)) val misa = RegInit(UInt(XLEN.W), misa_init.asUInt) // ISA寄存器 val mie = RegInit(0.U(XLEN.W)) // 中断使能寄存器 @@ -233,11 +229,9 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst { io.decoderUnit.interrupt := mie(11, 0) & mip_has_interrupt.asUInt & interrupt_enable.asUInt // 优先使用inst0的信息 - val exc_sel = - (HasExcInt(io.memoryUnit.in.inst(0).ex)) || !(HasExcInt(io.memoryUnit.in.inst(1).ex)) - val mem_pc = Mux(exc_sel, io.memoryUnit.in.inst(0).pc, io.memoryUnit.in.inst(1).pc) - val mem_ex = Mux(exc_sel, io.memoryUnit.in.inst(0).ex, io.memoryUnit.in.inst(1).ex) - val mem_inst_info = Mux(exc_sel, io.memoryUnit.in.inst(0).info, io.memoryUnit.in.inst(1).info) + val mem_pc = io.memoryUnit.in.pc + val mem_ex = io.memoryUnit.in.ex + val mem_inst_info = io.memoryUnit.in.info val mem_inst = mem_inst_info.inst val mem_valid = mem_inst_info.valid val mem_addr = mem_inst(31, 20) @@ -246,13 +240,13 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst { val has_interrupt = mem_ex.interrupt.asUInt.orR val has_exc_int = has_exception || has_interrupt // 不带前缀的信号为exe阶段的信号 - val valid = io.executeUnit.in.valid && !has_exc_int - val info = io.executeUnit.in.info - val op = io.executeUnit.in.info.op - val fusel = io.executeUnit.in.info.fusel - val addr = io.executeUnit.in.info.inst(31, 20) - val src1 = io.executeUnit.in.src_info.src1_data - val csri = ZeroExtend(io.executeUnit.in.info.inst(19, 15), XLEN) + val valid = io.executeUnit.in.valid && !has_exc_int + val info = io.executeUnit.in.info + val op = io.executeUnit.in.info.op + val fusel = io.executeUnit.in.info.fusel + val addr = io.executeUnit.in.info.inst(31, 20) + val src1 = io.executeUnit.in.src_info.src1_data + val csri = ZeroExtend(io.executeUnit.in.info.inst(19, 15), XLEN) wdata := LookupTree( op, List( diff --git a/chisel/playground/src/pipeline/memory/MemoryUnit.scala b/chisel/playground/src/pipeline/memory/MemoryUnit.scala index fef9b28..e17367a 100644 --- a/chisel/playground/src/pipeline/memory/MemoryUnit.scala +++ b/chisel/playground/src/pipeline/memory/MemoryUnit.scala @@ -92,19 +92,29 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module { io.writeBackStage.inst1.commit := io.memoryStage.inst1.info.valid && !(HasExcInt(io.writeBackStage.inst0.ex)) - io.csr.in.inst(0).pc := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst0.pc, 0.U) - io.csr.in.inst(0).ex := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst0.ex, 0.U.asTypeOf(new ExceptionInfo())) - io.csr.in.inst(0).info := Mux( - io.ctrl.allow_to_go, - io.writeBackStage.inst0.info, - 0.U.asTypeOf(new InstInfo()) + val csr_sel = + HasExcInt(io.writeBackStage.inst0.ex) || !HasExcInt(io.writeBackStage.inst1.ex) + + io.csr.in.pc := MuxCase( + 0.U, + Seq( + (io.ctrl.allow_to_go && csr_sel) -> io.writeBackStage.inst0.pc, + (io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst1.pc + ) ) - io.csr.in.inst(1).pc := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst1.pc, 0.U) - io.csr.in.inst(1).ex := Mux(io.ctrl.allow_to_go, io.writeBackStage.inst1.ex, 0.U.asTypeOf(new ExceptionInfo())) - io.csr.in.inst(1).info := Mux( - io.ctrl.allow_to_go, - io.writeBackStage.inst1.info, - 0.U.asTypeOf(new InstInfo()) + io.csr.in.ex := MuxCase( + 0.U.asTypeOf(new ExceptionInfo()), + Seq( + (io.ctrl.allow_to_go && csr_sel) -> io.writeBackStage.inst0.ex, + (io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst1.ex + ) + ) + io.csr.in.info := MuxCase( + 0.U.asTypeOf(new InstInfo()), + Seq( + (io.ctrl.allow_to_go && csr_sel) -> io.writeBackStage.inst0.info, + (io.ctrl.allow_to_go && !csr_sel) -> io.writeBackStage.inst1.info + ) ) io.csr.in.set_lr := dataMemoryAccess.memoryUnit.out.set_lr && io.ctrl.allow_to_go