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fix(dcache): 解决写请求发生了两次的问题

This commit is contained in:
Liphen 2023-12-07 17:04:04 +08:00
parent ff56c013ef
commit 9524ee9919
3 changed files with 4 additions and 4 deletions
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2
chisel/playground/src/cache/DCache.scala vendored
View File

@ -122,7 +122,7 @@ class DCache(implicit config: CpuConfig) extends Module {
} }
when(io.axi.b.valid) { when(io.axi.b.valid) {
acc_err := io.axi.b.resp =/= RESP_OKEY.U acc_err := io.axi.b.resp =/= RESP_OKEY.U
status := s_idle status := s_save
} }
} }
is(s_save) { is(s_save) {

4
chisel/playground/src/pipeline/memory/AtomAlu.scala
View File

@ -10,7 +10,7 @@ class AtomAlu extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val in = Input(new Bundle { val in = Input(new Bundle {
val rdata = Input(UInt(XLEN.W)) // load data val rdata = Input(UInt(XLEN.W)) // load data
val wdata = Input(UInt(XLEN.W)) // reg data val src2 = Input(UInt(XLEN.W)) // reg data
val info = new InstInfo() val info = new InstInfo()
}) })
val out = Output(new Bundle { val out = Output(new Bundle {
@ -19,7 +19,7 @@ class AtomAlu extends Module {
}) })
val src1 = io.in.rdata val src1 = io.in.rdata
val src2 = io.in.wdata val src2 = io.in.src2
val op = io.in.info.op val op = io.in.info.op
val is_sub = !LSUOpType.isAdd(op) val is_sub = !LSUOpType.isAdd(op)
val sum = (src1 +& (src2 ^ Fill(XLEN, is_sub))) + is_sub val sum = (src1 +& (src2 ^ Fill(XLEN, is_sub))) + is_sub

2
chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
View File

@ -92,7 +92,7 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
val atomMemReg = Reg(UInt(XLEN.W)) val atomMemReg = Reg(UInt(XLEN.W))
val atomRegReg = Reg(UInt(XLEN.W)) val atomRegReg = Reg(UInt(XLEN.W))
atomAlu.in.rdata := atomMemReg atomAlu.in.rdata := atomMemReg
atomAlu.in.wdata := io.dataMemory.out.wdata atomAlu.in.src2 := src2
atomAlu.in.info := io.memoryUnit.in.info atomAlu.in.info := io.memoryUnit.in.info
val scInvalid = (src1 =/= lrAddr || !lr) && scReq val scInvalid = (src1 =/= lrAddr || !lr) && scReq