diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala
index 614cd13..5346cf0 100644
--- a/chisel/playground/src/cache/DCache.scala
+++ b/chisel/playground/src/cache/DCache.scala
@@ -122,7 +122,7 @@ class DCache(implicit config: CpuConfig) extends Module {
       }
       when(io.axi.b.valid) {
         acc_err := io.axi.b.resp =/= RESP_OKEY.U
-        status  := s_idle
+        status  := s_save
       }
     }
     is(s_save) {
diff --git a/chisel/playground/src/pipeline/memory/AtomAlu.scala b/chisel/playground/src/pipeline/memory/AtomAlu.scala
index 2f6b4ea..1f3ffc0 100644
--- a/chisel/playground/src/pipeline/memory/AtomAlu.scala
+++ b/chisel/playground/src/pipeline/memory/AtomAlu.scala
@@ -10,7 +10,7 @@ class AtomAlu extends Module {
   val io = IO(new Bundle {
     val in = Input(new Bundle {
       val rdata = Input(UInt(XLEN.W)) // load data
-      val wdata = Input(UInt(XLEN.W)) // reg data
+      val src2  = Input(UInt(XLEN.W)) // reg data
       val info  = new InstInfo()
     })
     val out = Output(new Bundle {
@@ -19,7 +19,7 @@ class AtomAlu extends Module {
   })
 
   val src1    = io.in.rdata
-  val src2    = io.in.wdata
+  val src2    = io.in.src2
   val op      = io.in.info.op
   val is_sub  = !LSUOpType.isAdd(op)
   val sum     = (src1 +& (src2 ^ Fill(XLEN, is_sub))) + is_sub
diff --git a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
index 950cc74..29bc48b 100644
--- a/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
+++ b/chisel/playground/src/pipeline/memory/DataMemoryAccess.scala
@@ -92,7 +92,7 @@ class DataMemoryAccess(implicit val config: CpuConfig) extends Module {
   val atomMemReg = Reg(UInt(XLEN.W))
   val atomRegReg = Reg(UInt(XLEN.W))
   atomAlu.in.rdata := atomMemReg
-  atomAlu.in.wdata := io.dataMemory.out.wdata
+  atomAlu.in.src2  := src2
   atomAlu.in.info  := io.memoryUnit.in.info
 
   val scInvalid = (src1 =/= lrAddr || !lr) && scReq