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fix(ExeAccessMem): 修复mem en信号错误

This commit is contained in:
Liphen 2023-11-26 15:43:30 +08:00
parent 10cca9929b
commit 94352e1687
4 changed files with 38 additions and 38 deletions
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4
chisel/playground/src/Core.scala
View File

@ -44,7 +44,7 @@ class Core(implicit val config: CpuConfig) extends Module {
ctrl.memoryUnit <> memoryUnit.ctrl ctrl.memoryUnit <> memoryUnit.ctrl
ctrl.writeBackUnit <> writeBackUnit.ctrl ctrl.writeBackUnit <> writeBackUnit.ctrl
ctrl.cacheCtrl.iCache_stall := io.inst.icache_stall ctrl.cacheCtrl.iCache_stall := io.inst.icache_stall
ctrl.cacheCtrl.dCache_stall := io.data.stall ctrl.cacheCtrl.dCache_stall := io.data.dcache_stall
fetchUnit.memory <> memoryUnit.fetchUnit fetchUnit.memory <> memoryUnit.fetchUnit
fetchUnit.execute <> executeUnit.fetchUnit fetchUnit.execute <> executeUnit.fetchUnit
@ -143,5 +143,5 @@ class Core(implicit val config: CpuConfig) extends Module {
memoryUnit.memoryStage.inst0.inst_info.op === MOUOpType.fencei memoryUnit.memoryStage.inst0.inst_info.op === MOUOpType.fencei
io.inst.req := !instFifo.full && !reset.asBool io.inst.req := !instFifo.full && !reset.asBool
io.inst.cpu_ready := ctrl.fetchUnit.allow_to_go io.inst.cpu_ready := ctrl.fetchUnit.allow_to_go
io.data.ready := ctrl.memoryUnit.allow_to_go io.data.cpu_ready := ctrl.memoryUnit.allow_to_go
} }

44
chisel/playground/src/cache/DCache.scala vendored
View File

@ -15,8 +15,8 @@ class DCache(implicit config: CpuConfig) extends Module {
}) })
// * fsm * // // * fsm * //
val s_idle :: s_read :: s_write :: s_finishwait :: Nil = Enum(4) val s_idle :: s_uncached :: s_writeback :: s_save :: Nil = Enum(4)
val status = RegInit(s_idle) val status = RegInit(s_idle)
val wstrb_gen = Wire(UInt(8.W)) val wstrb_gen = Wire(UInt(8.W))
wstrb_gen := MuxLookup(io.cpu.size, "b1111_1111".U)( wstrb_gen := MuxLookup(io.cpu.size, "b1111_1111".U)(
@ -28,7 +28,7 @@ class DCache(implicit config: CpuConfig) extends Module {
) )
) )
io.cpu.valid := status === s_finishwait io.cpu.valid := status === s_save
val addr_err = io.cpu.addr(63, 32).orR val addr_err = io.cpu.addr(63, 32).orR
@ -54,13 +54,13 @@ class DCache(implicit config: CpuConfig) extends Module {
io.axi.ar.size := 0.U io.axi.ar.size := 0.U
io.axi.ar.burst := BURST_FIXED.U io.axi.ar.burst := BURST_FIXED.U
val arvalid = RegInit(false.B) val arvalid = RegInit(false.B)
io.axi.ar.valid := arvalid io.axi.ar.valid := arvalid
io.axi.ar.prot := 0.U io.axi.ar.prot := 0.U
io.axi.ar.cache := 0.U io.axi.ar.cache := 0.U
io.axi.ar.lock := 0.U io.axi.ar.lock := 0.U
io.axi.r.ready := true.B io.axi.r.ready := true.B
io.cpu.rdata := 0.U io.cpu.rdata := 0.U
io.cpu.stall := false.B io.cpu.dcache_stall := status === s_uncached
io.cpu.acc_err := false.B io.cpu.acc_err := false.B
@ -69,7 +69,7 @@ class DCache(implicit config: CpuConfig) extends Module {
when(io.cpu.en) { when(io.cpu.en) {
when(addr_err) { when(addr_err) {
io.cpu.acc_err := true.B io.cpu.acc_err := true.B
status := s_finishwait status := s_save
}.otherwise { }.otherwise {
when(io.cpu.write) { when(io.cpu.write) {
io.axi.aw.addr := io.cpu.addr(31, 0) io.axi.aw.addr := io.cpu.addr(31, 0)
@ -78,27 +78,27 @@ class DCache(implicit config: CpuConfig) extends Module {
io.axi.w.data := io.cpu.wdata io.axi.w.data := io.cpu.wdata
io.axi.w.strb := wstrb_gen io.axi.w.strb := wstrb_gen
io.axi.w.valid := true.B io.axi.w.valid := true.B
status := s_write status := s_writeback
}.otherwise { }.otherwise {
io.axi.ar.addr := io.cpu.addr(31, 0) io.axi.ar.addr := io.cpu.addr(31, 0)
io.axi.ar.size := Cat(false.B, io.cpu.size) io.axi.ar.size := Cat(false.B, io.cpu.size)
arvalid := true.B arvalid := true.B
status := s_read status := s_uncached
} }
} }
} }
} }
is(s_read) { is(s_uncached) {
when(io.axi.ar.ready) { when(io.axi.ar.ready) {
arvalid := false.B arvalid := false.B
} }
when(io.axi.r.valid) { when(io.axi.r.valid) {
io.cpu.rdata := io.axi.r.data io.cpu.rdata := io.axi.r.data
io.cpu.acc_err := io.axi.r.resp =/= RESP_OKEY.U io.cpu.acc_err := io.axi.r.resp =/= RESP_OKEY.U
status := s_finishwait status := s_save
} }
} }
is(s_write) { is(s_writeback) {
when(io.axi.aw.ready) { when(io.axi.aw.ready) {
io.axi.aw.valid := false.B io.axi.aw.valid := false.B
} }
@ -107,16 +107,16 @@ class DCache(implicit config: CpuConfig) extends Module {
} }
when(io.axi.b.valid) { when(io.axi.b.valid) {
io.cpu.acc_err := io.axi.b.resp =/= RESP_OKEY.U io.cpu.acc_err := io.axi.b.resp =/= RESP_OKEY.U
status := s_finishwait status := s_save
} }
} }
is(s_finishwait) { is(s_save) {
when(io.cpu.ready) { when(io.cpu.cpu_ready) {
io.cpu.acc_err := false.B io.cpu.acc_err := false.B
when(io.cpu.en) { when(io.cpu.en) {
when(addr_err) { when(addr_err) {
io.cpu.acc_err := true.B io.cpu.acc_err := true.B
status := s_finishwait status := s_save
}.otherwise { }.otherwise {
when(io.cpu.write) { when(io.cpu.write) {
io.axi.aw.addr := io.cpu.addr(31, 0) io.axi.aw.addr := io.cpu.addr(31, 0)
@ -125,12 +125,12 @@ class DCache(implicit config: CpuConfig) extends Module {
io.axi.w.data := io.cpu.wdata io.axi.w.data := io.cpu.wdata
io.axi.w.strb := wstrb_gen io.axi.w.strb := wstrb_gen
io.axi.w.valid := true.B io.axi.w.valid := true.B
status := s_write status := s_writeback
}.otherwise { }.otherwise {
io.axi.ar.addr := io.cpu.addr(31, 0) io.axi.ar.addr := io.cpu.addr(31, 0)
io.axi.ar.size := Cat(false.B, io.cpu.size) io.axi.ar.size := Cat(false.B, io.cpu.size)
arvalid := true.B arvalid := true.B
status := s_read status := s_uncached
} }
} }
}.otherwise { }.otherwise {

22
chisel/playground/src/defines/Bundles.scala
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@ -123,18 +123,18 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle {
// cpu to dcache // cpu to dcache
class Cache_DCache extends Bundle { class Cache_DCache extends Bundle {
val addr = Output(UInt(DATA_ADDR_WID.W)) val addr = Output(UInt(DATA_ADDR_WID.W))
val size = Output(UInt(2.W)) val size = Output(UInt(2.W))
val en = Output(Bool()) val en = Output(Bool())
val write = Output(Bool()) val write = Output(Bool())
val wdata = Output(UInt(XLEN.W)) val wdata = Output(UInt(XLEN.W))
val ready = Output(Bool()) val cpu_ready = Output(Bool())
val fence_i = Output(Bool()) val fence_i = Output(Bool())
val rdata = Input(UInt(XLEN.W)) val rdata = Input(UInt(XLEN.W))
val valid = Input(Bool()) val valid = Input(Bool())
val acc_err = Input(Bool()) val acc_err = Input(Bool())
val stall = Input(Bool()) val dcache_stall = Input(Bool())
} }
// axi // axi

6
chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
View File

@ -75,13 +75,13 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
for (i <- 0 until config.fuNum) { for (i <- 0 until config.fuNum) {
val store_inst = LSUOpType.isStore(io.inst(i).inst_info.op) val store_inst = LSUOpType.isStore(io.inst(i).inst_info.op)
io.inst(i).ex.out := io.inst(i).ex.in io.inst(i).ex.out := io.inst(i).ex.in
io.inst(i).ex.out.exception(loadAddrMisaligned) := store_inst && !addr_aligned(i) io.inst(i).ex.out.exception(loadAddrMisaligned) := store_inst && !addr_aligned(i)
io.inst(i).ex.out.exception(storeAddrMisaligned) := !store_inst && !addr_aligned(i) io.inst(i).ex.out.exception(storeAddrMisaligned) := !store_inst && !addr_aligned(i)
} }
io.inst(0).mem_sel := (LSUOpType.isStore(io.inst(0).inst_info.op) || LSUOpType.isLoad(io.inst(0).inst_info.op)) && io.inst(0).mem_sel := (io.inst(0).inst_info.fusel === FuType.lsu) &&
!io.inst(0).ex.out.exception.asUInt.orR && io.inst(0).inst_info.valid !io.inst(0).ex.out.exception.asUInt.orR && io.inst(0).inst_info.valid
io.inst(1).mem_sel := (LSUOpType.isStore(io.inst(1).inst_info.op) || LSUOpType.isLoad(io.inst(1).inst_info.op)) && io.inst(1).mem_sel := (io.inst(1).inst_info.fusel === FuType.lsu) &&
!io.inst(0).ex.out.exception.asUInt.orR && !io.inst(1).ex.out.exception.asUInt.orR && io.inst(1).inst_info.valid !io.inst(0).ex.out.exception.asUInt.orR && !io.inst(1).ex.out.exception.asUInt.orR && io.inst(1).inst_info.valid
} }