From 94352e16870492d5bd80dd778f3d0b181bc8a09e Mon Sep 17 00:00:00 2001 From: Liphen Date: Sun, 26 Nov 2023 15:43:30 +0800 Subject: [PATCH] =?UTF-8?q?fix(ExeAccessMem):=20=E4=BF=AE=E5=A4=8Dmem=20en?= =?UTF-8?q?=E4=BF=A1=E5=8F=B7=E9=94=99=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/Core.scala | 4 +- chisel/playground/src/cache/DCache.scala | 44 +++++++++---------- chisel/playground/src/defines/Bundles.scala | 22 +++++----- .../pipeline/execute/ExeAccessMemCtrl.scala | 6 +-- 4 files changed, 38 insertions(+), 38 deletions(-) diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala index 79cbcf4..1556c9f 100644 --- a/chisel/playground/src/Core.scala +++ b/chisel/playground/src/Core.scala @@ -44,7 +44,7 @@ class Core(implicit val config: CpuConfig) extends Module { ctrl.memoryUnit <> memoryUnit.ctrl ctrl.writeBackUnit <> writeBackUnit.ctrl ctrl.cacheCtrl.iCache_stall := io.inst.icache_stall - ctrl.cacheCtrl.dCache_stall := io.data.stall + ctrl.cacheCtrl.dCache_stall := io.data.dcache_stall fetchUnit.memory <> memoryUnit.fetchUnit fetchUnit.execute <> executeUnit.fetchUnit @@ -143,5 +143,5 @@ class Core(implicit val config: CpuConfig) extends Module { memoryUnit.memoryStage.inst0.inst_info.op === MOUOpType.fencei io.inst.req := !instFifo.full && !reset.asBool io.inst.cpu_ready := ctrl.fetchUnit.allow_to_go - io.data.ready := ctrl.memoryUnit.allow_to_go + io.data.cpu_ready := ctrl.memoryUnit.allow_to_go } diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala index 1b1d61f..3789111 100644 --- a/chisel/playground/src/cache/DCache.scala +++ b/chisel/playground/src/cache/DCache.scala @@ -15,8 +15,8 @@ class DCache(implicit config: CpuConfig) extends Module { }) // * fsm * // - val s_idle :: s_read :: s_write :: s_finishwait :: Nil = Enum(4) - val status = RegInit(s_idle) + val s_idle :: s_uncached :: s_writeback :: s_save :: Nil = Enum(4) + val status = RegInit(s_idle) val wstrb_gen = Wire(UInt(8.W)) wstrb_gen := MuxLookup(io.cpu.size, "b1111_1111".U)( @@ -28,7 +28,7 @@ class DCache(implicit config: CpuConfig) extends Module { ) ) - io.cpu.valid := status === s_finishwait + io.cpu.valid := status === s_save val addr_err = io.cpu.addr(63, 32).orR @@ -54,13 +54,13 @@ class DCache(implicit config: CpuConfig) extends Module { io.axi.ar.size := 0.U io.axi.ar.burst := BURST_FIXED.U val arvalid = RegInit(false.B) - io.axi.ar.valid := arvalid - io.axi.ar.prot := 0.U - io.axi.ar.cache := 0.U - io.axi.ar.lock := 0.U - io.axi.r.ready := true.B - io.cpu.rdata := 0.U - io.cpu.stall := false.B + io.axi.ar.valid := arvalid + io.axi.ar.prot := 0.U + io.axi.ar.cache := 0.U + io.axi.ar.lock := 0.U + io.axi.r.ready := true.B + io.cpu.rdata := 0.U + io.cpu.dcache_stall := status === s_uncached io.cpu.acc_err := false.B @@ -69,7 +69,7 @@ class DCache(implicit config: CpuConfig) extends Module { when(io.cpu.en) { when(addr_err) { io.cpu.acc_err := true.B - status := s_finishwait + status := s_save }.otherwise { when(io.cpu.write) { io.axi.aw.addr := io.cpu.addr(31, 0) @@ -78,27 +78,27 @@ class DCache(implicit config: CpuConfig) extends Module { io.axi.w.data := io.cpu.wdata io.axi.w.strb := wstrb_gen io.axi.w.valid := true.B - status := s_write + status := s_writeback }.otherwise { io.axi.ar.addr := io.cpu.addr(31, 0) io.axi.ar.size := Cat(false.B, io.cpu.size) arvalid := true.B - status := s_read + status := s_uncached } } } } - is(s_read) { + is(s_uncached) { when(io.axi.ar.ready) { arvalid := false.B } when(io.axi.r.valid) { io.cpu.rdata := io.axi.r.data io.cpu.acc_err := io.axi.r.resp =/= RESP_OKEY.U - status := s_finishwait + status := s_save } } - is(s_write) { + is(s_writeback) { when(io.axi.aw.ready) { io.axi.aw.valid := false.B } @@ -107,16 +107,16 @@ class DCache(implicit config: CpuConfig) extends Module { } when(io.axi.b.valid) { io.cpu.acc_err := io.axi.b.resp =/= RESP_OKEY.U - status := s_finishwait + status := s_save } } - is(s_finishwait) { - when(io.cpu.ready) { + is(s_save) { + when(io.cpu.cpu_ready) { io.cpu.acc_err := false.B when(io.cpu.en) { when(addr_err) { io.cpu.acc_err := true.B - status := s_finishwait + status := s_save }.otherwise { when(io.cpu.write) { io.axi.aw.addr := io.cpu.addr(31, 0) @@ -125,12 +125,12 @@ class DCache(implicit config: CpuConfig) extends Module { io.axi.w.data := io.cpu.wdata io.axi.w.strb := wstrb_gen io.axi.w.valid := true.B - status := s_write + status := s_writeback }.otherwise { io.axi.ar.addr := io.cpu.addr(31, 0) io.axi.ar.size := Cat(false.B, io.cpu.size) arvalid := true.B - status := s_read + status := s_uncached } } }.otherwise { diff --git a/chisel/playground/src/defines/Bundles.scala b/chisel/playground/src/defines/Bundles.scala index 2002d7f..635b293 100644 --- a/chisel/playground/src/defines/Bundles.scala +++ b/chisel/playground/src/defines/Bundles.scala @@ -123,18 +123,18 @@ class Cache_ICache(implicit val config: CpuConfig) extends Bundle { // cpu to dcache class Cache_DCache extends Bundle { - val addr = Output(UInt(DATA_ADDR_WID.W)) - val size = Output(UInt(2.W)) - val en = Output(Bool()) - val write = Output(Bool()) - val wdata = Output(UInt(XLEN.W)) - val ready = Output(Bool()) - val fence_i = Output(Bool()) + val addr = Output(UInt(DATA_ADDR_WID.W)) + val size = Output(UInt(2.W)) + val en = Output(Bool()) + val write = Output(Bool()) + val wdata = Output(UInt(XLEN.W)) + val cpu_ready = Output(Bool()) + val fence_i = Output(Bool()) - val rdata = Input(UInt(XLEN.W)) - val valid = Input(Bool()) - val acc_err = Input(Bool()) - val stall = Input(Bool()) + val rdata = Input(UInt(XLEN.W)) + val valid = Input(Bool()) + val acc_err = Input(Bool()) + val dcache_stall = Input(Bool()) } // axi diff --git a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala index e1ef7aa..7cfcad6 100644 --- a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala +++ b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala @@ -75,13 +75,13 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module { for (i <- 0 until config.fuNum) { val store_inst = LSUOpType.isStore(io.inst(i).inst_info.op) - io.inst(i).ex.out := io.inst(i).ex.in + io.inst(i).ex.out := io.inst(i).ex.in io.inst(i).ex.out.exception(loadAddrMisaligned) := store_inst && !addr_aligned(i) io.inst(i).ex.out.exception(storeAddrMisaligned) := !store_inst && !addr_aligned(i) } - io.inst(0).mem_sel := (LSUOpType.isStore(io.inst(0).inst_info.op) || LSUOpType.isLoad(io.inst(0).inst_info.op)) && + io.inst(0).mem_sel := (io.inst(0).inst_info.fusel === FuType.lsu) && !io.inst(0).ex.out.exception.asUInt.orR && io.inst(0).inst_info.valid - io.inst(1).mem_sel := (LSUOpType.isStore(io.inst(1).inst_info.op) || LSUOpType.isLoad(io.inst(1).inst_info.op)) && + io.inst(1).mem_sel := (io.inst(1).inst_info.fusel === FuType.lsu) && !io.inst(0).ex.out.exception.asUInt.orR && !io.inst(1).ex.out.exception.asUInt.orR && io.inst(1).inst_info.valid }