refactor: 删除PC_WID

chisel/playground/src/cache/mmu/ITlbL1.scala

@@ -7,7 +7,7 @@ import cpu.defines.Const._
 
 class ITlbL1 extends Module {
   val io = IO(new Bundle {
-    val addr  = Input(UInt(PC_WID.W))
+    val addr  = Input(UInt(XLEN.W))
     val cache = new Tlb_ICache()
   })
 

chisel/playground/src/defines/Bundles.scala

@@ -207,7 +207,7 @@ class AXI extends Bundle {
 }
 
 class DEBUG extends Bundle {
-  val wb_pc       = Output(UInt(PC_WID.W))
+  val wb_pc       = Output(UInt(XLEN.W))
   val wb_rf_wen   = Output(Bool())
   val wb_rf_wnum  = Output(UInt(REG_ADDR_WID.W))
   val wb_rf_wdata = Output(UInt(XLEN.W))

chisel/playground/src/defines/Const.scala

@@ -13,8 +13,7 @@ trait CoreParameter {
 
 trait Constants extends CoreParameter {
   // 全局
-  val PC_WID  = XLEN
-  val PC_INIT = "h80000000".U(PC_WID.W)
+  val PC_INIT = "h80000000".U(XLEN.W)
 
   val INT_WID = 12
   val EXC_WID = 16

chisel/playground/src/defines/TlbBundles.scala

@@ -125,7 +125,6 @@ class Tlb_ICache extends Bundle {
 
 class Tlb_DCache extends Bundle {
   val fill           = Input(Bool())
-  val dcache_is_idle = Input(Bool())
   val uncached       = Output(Bool())
   val tlb1_ok        = Output(Bool())
 

chisel/playground/src/pipeline/decoder/DecoderUnit.scala

@@ -27,13 +27,13 @@ class DataForwardToDecoderUnit extends Bundle {
 
 class DecoderBranchPredictorUnit extends Bundle {
   val bpuConfig = new BranchPredictorConfig()
-  val pc        = Output(UInt(PC_WID.W))
+  val pc        = Output(UInt(XLEN.W))
   val info      = Output(new InstInfo())
   val pht_index = Output(UInt(bpuConfig.phtDepth.W))
 
   val branch_inst      = Input(Bool())
   val pred_branch      = Input(Bool())
-  val branch_target    = Input(UInt(PC_WID.W))
+  val branch_target    = Input(UInt(XLEN.W))
   val update_pht_index = Input(UInt(bpuConfig.phtDepth.W))
 }
 
@@ -47,7 +47,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
     // 输出
     val fetchUnit = new Bundle {
       val branch = Output(Bool())
-      val target = Output(UInt(PC_WID.W))
+      val target = Output(UInt(XLEN.W))
     }
     val bpu          = new DecoderBranchPredictorUnit()
     val executeStage = Output(new DecoderUnitExecuteUnit())

chisel/playground/src/pipeline/decoder/JumpCtrl.scala

@@ -10,7 +10,7 @@ import cpu.CpuConfig
 class JumpCtrl(implicit val config: CpuConfig) extends Module {
   val io = IO(new Bundle {
     val in = Input(new Bundle {
-      val pc       = UInt(PC_WID.W)
+      val pc       = UInt(XLEN.W)
       val info     = new InstInfo()
       val src_info = new SrcInfo()
       val forward  = Vec(config.commitNum, new DataForwardToDecoderUnit())
@@ -19,7 +19,7 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module {
       val jump_inst     = Bool()
       val jump_register = Bool()
       val jump          = Bool()
-      val jump_target   = UInt(PC_WID.W)
+      val jump_target   = UInt(XLEN.W)
     })
   })
 

chisel/playground/src/pipeline/execute/BranchCtrl.scala

@@ -8,17 +8,17 @@ import cpu.defines.Const._
 class BranchCtrl extends Module {
   val io = IO(new Bundle {
     val in = new Bundle {
-      val pc            = Input(UInt(PC_WID.W))
+      val pc            = Input(UInt(XLEN.W))
       val info          = Input(new InstInfo())
       val src_info      = Input(new SrcInfo())
       val pred_branch   = Input(Bool())
       val jump_regiser  = Input(Bool())
-      val branch_target = Input(UInt(PC_WID.W))
+      val branch_target = Input(UInt(XLEN.W))
     }
     val out = new Bundle {
       val branch    = Output(Bool())
       val pred_fail = Output(Bool())
-      val target    = Output(UInt(PC_WID.W))
+      val target    = Output(UInt(XLEN.W))
     }
   })
   val valid =

chisel/playground/src/pipeline/execute/Csr.scala

@@ -9,7 +9,7 @@ import chisel3.util.experimental.BoringUtils
 
 class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
   val in = Input(new Bundle {
-    val pc   = UInt(PC_WID.W)
+    val pc   = UInt(XLEN.W)
     val ex   = new ExceptionInfo()
     val info = new InstInfo()
 
@@ -19,7 +19,7 @@ class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
   })
   val out = Output(new Bundle {
     val flush    = Bool()
-    val flush_pc = UInt(PC_WID.W)
+    val flush_pc = UInt(XLEN.W)
 
     val lr      = Bool()
     val lr_addr = UInt(DATA_ADDR_WID.W)

chisel/playground/src/pipeline/execute/ExecuteStage.scala

@@ -8,7 +8,7 @@ import cpu.{BranchPredictorConfig, CpuConfig}
 
 class IdExeInst0 extends Bundle {
   val config   = new BranchPredictorConfig()
-  val pc       = UInt(PC_WID.W)
+  val pc       = UInt(XLEN.W)
   val info     = new InstInfo()
   val src_info = new SrcInfo()
   val ex       = new ExceptionInfo()
@@ -18,13 +18,13 @@ class IdExeInst0 extends Bundle {
     // bpu
     val branch_inst      = Bool()
     val pred_branch      = Bool()
-    val branch_target    = UInt(PC_WID.W)
+    val branch_target    = UInt(XLEN.W)
     val update_pht_index = UInt(config.phtDepth.W)
   }
 }
 
 class IdExeInst1 extends Bundle {
-  val pc          = UInt(PC_WID.W)
+  val pc          = UInt(XLEN.W)
   val info        = new InstInfo()
   val src_info    = new SrcInfo()
   val ex          = new ExceptionInfo()

chisel/playground/src/pipeline/execute/ExecuteUnit.scala

@@ -17,7 +17,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
     val bpu          = new ExecuteUnitBranchPredictor()
     val fetchUnit = Output(new Bundle {
       val flush  = Bool()
-      val target = UInt(PC_WID.W)
+      val target = UInt(XLEN.W)
     })
     val decoderUnit = new Bundle {
       val forward = Output(

chisel/playground/src/pipeline/execute/Fu.scala

@@ -12,7 +12,7 @@ class Fu(implicit val config: CpuConfig) extends Module {
     val inst = Vec(
       config.decoderNum,
       new Bundle {
-        val pc       = Input(UInt(PC_WID.W))
+        val pc       = Input(UInt(XLEN.W))
         val info     = Input(new InstInfo())
         val src_info = Input(new SrcInfo())
         val result = Output(new Bundle {
@@ -25,10 +25,10 @@ class Fu(implicit val config: CpuConfig) extends Module {
     val branch = new Bundle {
       val pred_branch   = Input(Bool())
       val jump_regiser  = Input(Bool())
-      val branch_target = Input(UInt(PC_WID.W))
+      val branch_target = Input(UInt(XLEN.W))
       val branch        = Output(Bool())
       val flush         = Output(Bool())
-      val target        = Output(UInt(PC_WID.W))
+      val target        = Output(UInt(XLEN.W))
     }
   })
 

chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala

@@ -13,7 +13,7 @@ import cpu.pipeline.decoder.DecoderBranchPredictorUnit
 
 class ExecuteUnitBranchPredictor extends Bundle {
   val bpuConfig        = new BranchPredictorConfig()
-  val pc               = Output(UInt(PC_WID.W))
+  val pc               = Output(UInt(XLEN.W))
   val update_pht_index = Output(UInt(bpuConfig.phtDepth.W))
   val branch_inst      = Output(Bool())
   val branch           = Output(Bool())
@@ -24,7 +24,7 @@ class BranchPredictorIO(implicit config: CpuConfig) extends Bundle {
   val decoder   = Flipped(new DecoderBranchPredictorUnit())
 
   val instBuffer = new Bundle {
-    val pc        = Input(Vec(config.instFetchNum, UInt(PC_WID.W)))
+    val pc        = Input(Vec(config.instFetchNum, UInt(XLEN.W)))
     val pht_index = Output(Vec(config.instFetchNum, UInt(bpuConfig.phtDepth.W)))
   }
 

chisel/playground/src/pipeline/fetch/FetchUnit.scala

@@ -12,23 +12,23 @@ class FetchUnit(
   val io = IO(new Bundle {
     val memory = new Bundle {
       val flush  = Input(Bool())
-      val target = Input(UInt(PC_WID.W))
+      val target = Input(UInt(XLEN.W))
     }
     val decoder = new Bundle {
       val branch = Input(Bool())
-      val target = Input(UInt(PC_WID.W))
+      val target = Input(UInt(XLEN.W))
     }
     val execute = new Bundle {
       val flush  = Input(Bool())
-      val target = Input(UInt(PC_WID.W))
+      val target = Input(UInt(XLEN.W))
     }
     val instFifo = new Bundle {
       val full = Input(Bool())
     }
     val iCache = new Bundle {
       val inst_valid = Input(Vec(config.instFetchNum, Bool()))
-      val pc         = Output(UInt(PC_WID.W))
-      val pc_next    = Output(UInt(PC_WID.W))
+      val pc         = Output(UInt(XLEN.W))
+      val pc_next    = Output(UInt(XLEN.W))
     }
 
   })
@@ -37,7 +37,7 @@ class FetchUnit(
 
   // when inst_valid(1) is true, inst_valid(0) must be true
 
-  val pc_next_temp = Wire(UInt(PC_WID.W))
+  val pc_next_temp = Wire(UInt(XLEN.W))
 
   pc_next_temp := pc
   for (i <- 0 until config.instFetchNum) {

chisel/playground/src/pipeline/fetch/InstFifo.scala

@@ -10,7 +10,7 @@ class BufferUnit extends Bundle {
   val inst      = UInt(XLEN.W)
   val pht_index = UInt(bpuConfig.phtDepth.W)
   val acc_err   = Bool()
-  val pc        = UInt(PC_WID.W)
+  val pc        = UInt(XLEN.W)
 }
 
 class InstFifo(implicit val config: CpuConfig) extends Module {

chisel/playground/src/pipeline/memory/MemoryStage.scala

@@ -7,7 +7,7 @@ import cpu.defines.Const._
 import cpu.CpuConfig
 
 class ExeMemInst extends Bundle {
-  val pc       = UInt(PC_WID.W)
+  val pc       = UInt(XLEN.W)
   val info     = new InstInfo()
   val rd_info  = new RdInfo()
   val src_info = new SrcInfo()

chisel/playground/src/pipeline/memory/MemoryUnit.scala

@@ -15,7 +15,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
     val memoryStage = Input(new ExecuteUnitMemoryUnit())
     val fetchUnit = Output(new Bundle {
       val flush  = Bool()
-      val target = UInt(PC_WID.W)
+      val target = UInt(XLEN.W)
     })
     val decoderUnit    = Output(Vec(config.commitNum, new RegWrite()))
     val csr            = Flipped(new CsrMemoryUnit())

chisel/playground/src/pipeline/memory/Mou.scala

@@ -9,11 +9,11 @@ class Mou extends Module {
   val io = IO(new Bundle {
     val in = Input(new Bundle {
       val info = new InstInfo()
-      val pc   = UInt(PC_WID.W)
+      val pc   = UInt(XLEN.W)
     })
     val out = Output(new Bundle {
       val flush  = Bool()
-      val target = UInt(PC_WID.W)
+      val target = UInt(XLEN.W)
     })
   })
 

chisel/playground/src/pipeline/writeback/WriteBackStage.scala

@@ -7,7 +7,7 @@ import cpu.defines.Const._
 import cpu.CpuConfig
 
 class MemWbInst extends Bundle {
-  val pc      = UInt(PC_WID.W)
+  val pc      = UInt(XLEN.W)
   val info    = new InstInfo()
   val rd_info = new RdInfo()
   val ex      = new ExceptionInfo()