yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

生成idu

This commit is contained in:
Liphen 2023-11-19 16:17:59 +08:00
parent b509674610
commit 7ecb175c6d
9 changed files with 185 additions and 169 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
chisel/playground/src/Elaborate.scala
View File

@ -1,14 +1,14 @@
import cpu._
import circt.stage._
// import cpu._
// import circt.stage._
object Elaborate extends App {
implicit val config = new CpuConfig()
def top = new PuaCpu()
val useMFC = false // use MLIR-based firrtl compiler
val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
if (useMFC) {
(new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
} else {
(new chisel3.stage.ChiselStage).execute(args, generator)
}
}
// object Elaborate extends App {
// implicit val config = new CpuConfig()
// def top = new PuaCpu()
// val useMFC = false // use MLIR-based firrtl compiler
// val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
// if (useMFC) {
// (new ChiselStage).execute(args, generator :+ CIRCTTargetAnnotation(CIRCTTarget.Verilog))
// } else {
// (new chisel3.stage.ChiselStage).execute(args, generator)
// }
// }

40
chisel/playground/src/PuaCpu.scala
View File

@ -1,23 +1,23 @@
import chisel3._
import chisel3.util._
import cache._
import cpu._
import cpu.defines._
// import chisel3._
// import chisel3.util._
// import cache._
// import cpu._
// import cpu.defines._
class PuaCpu extends Module {
implicit val config = new CpuConfig()
val io = IO(new Bundle {
val ext_int = Input(UInt(6.W))
val axi = new AXI()
val debug = new DEBUG()
})
val core = Module(new Core())
val cache = Module(new Cache())
// class PuaCpu extends Module {
// implicit val config = new CpuConfig()
// val io = IO(new Bundle {
// val ext_int = Input(UInt(6.W))
// val axi = new AXI()
// val debug = new DEBUG()
// })
// val core = Module(new Core())
// val cache = Module(new Cache())
core.io.inst <> cache.io.inst
core.io.data <> cache.io.data
// core.io.inst <> cache.io.inst
// core.io.data <> cache.io.data
io.ext_int <> core.io.ext_int
io.debug <> core.io.debug
io.axi <> cache.io.axi
}
// io.ext_int <> core.io.ext_int
// io.debug <> core.io.debug
// io.axi <> cache.io.axi
// }

130
chisel/playground/src/defines/Const.scala
View File

@ -11,91 +11,91 @@ trait CoreParameter {
trait Constants extends CoreParameter {
// 全局
def PC_WID = XLEN
def PC_INIT = "h60000000".U(PC_WID.W)
val PC_WID = XLEN
val PC_INIT = "h60000000".U(PC_WID.W)
def SINGLE_ISSUE = false.B
def DUAL_ISSUE = true.B
val SINGLE_ISSUE = false.B
val DUAL_ISSUE = true.B
def INT_WID = 12
def EXCODE_WID = 16
val INT_WID = 12
val EXCODE_WID = 16
// div
def DIV_CTRL_WID = 2
def DIV_FREE = 0.U(DIV_CTRL_WID.W)
def DIV_BY_ZERO = 1.U(DIV_CTRL_WID.W)
def DIV_ON = 2.U(DIV_CTRL_WID.W)
def DIV_END = 3.U(DIV_CTRL_WID.W)
def DIV_RESULT_READY = true.B
def DIV_RESULT_NOT_READY = false.B
def DIV_START = true.B
def DIV_STOP = false.B
val DIV_CTRL_WID = 2
val DIV_FREE = 0.U(DIV_CTRL_WID.W)
val DIV_BY_ZERO = 1.U(DIV_CTRL_WID.W)
val DIV_ON = 2.U(DIV_CTRL_WID.W)
val DIV_END = 3.U(DIV_CTRL_WID.W)
val DIV_RESULT_READY = true.B
val DIV_RESULT_NOT_READY = false.B
val DIV_START = true.B
val DIV_STOP = false.B
// inst rom
def INST_WID = 32
def INST_ADDR_WID = PC_WID
val INST_WID = 32
val INST_ADDR_WID = PC_WID
// data ram
def DATA_ADDR_WID = PC_WID
val DATA_ADDR_WID = PC_WID
// GPR RegFile
def AREG_NUM = 32
def REG_ADDR_WID = 5
def DATA_WID = XLEN
val AREG_NUM = 32
val REG_ADDR_WID = 5
val DATA_WID = XLEN
// CSR寄存器
// CSR Register (5.w), Select (3.w)
def CSR_INDEX_ADDR = "b00000_000".U(8.W) // 0,0
def CSR_RANDOM_ADDR = "b00001_000".U(8.W) // 1,0
def CSR_ENTRYLO0_ADDR = "b00010_000".U(8.W) // 2,0
def CSR_ENTRYLO1_ADDR = "b00011_000".U(8.W) // 3,0
def CSR_CONTEXT_ADDR = "b00100_000".U(8.W) // 4,0
// def CSR_CONTEXT_CONFIG_ADDR = "b00100_001".U(8.W) // 4,1
// def CSR_USER_LOCAL_ADDR = "b00100_010".U(8.W) // 4,2
def CSR_PAGE_MASK_ADDR = "b00101_000".U(8.W) // 5,0
// def CSR_PAGE_GRAIN_ADDR = "b00101_001".U(8.W) // 5,1
def CSR_WIRED_ADDR = "b00110_000".U(8.W) // 6,0
// def CSR_HWRENA_ADDR = "b00111_000".U(8.W) // 7,0
def CSR_BADV_ADDR = "b01000_000".U(8.W) // 8,0
def CSR_COUNT_ADDR = "b01001_000".U(8.W) // 9,0 (sel保留 6or7)
def CSR_ENTRYHI_ADDR = "b01010_000".U(8.W) // 10,0
def CSR_COMPARE_ADDR = "b01011_000".U(8.W) // 11,0 (sel保留 6or7)
def CSR_STATUS_ADDR = "b01100_000".U(8.W) // 12,0
// def CSR_INTCTL_ADDR = "b01100_001".U(8.W) // 12,1
// def CSR_SRSCTL_ADDR = "b01100_010".U(8.W) // 12,2
// def CSR_SRSMAP_ADDR = "b01100_011".U(8.W) // 12,3
def CSR_CAUSE_ADDR = "b01101_000".U(8.W) // 13,0
def CSR_EPC_ADDR = "b01110_000".U(8.W) // 14,0
def CSR_PRID_ADDR = "b01111_000".U(8.W) // 15,0
def CSR_EBASE_ADDR = "b01111_001".U(8.W) // 15,1
// def CSR_CDMMBASE_ADDR = "b01111_010".U(8.W) // 15,2
// def CSR_CMGCRBASE_ADDR = "b01111_011".U(8.W) // 15,3
def CSR_CONFIG_ADDR = "b10000_000".U(8.W) // 16,0
def CSR_CONFIG1_ADDR = "b10000_001".U(8.W) // 16,1
// def CSR_CONFIG2_ADDR = "b10000_010".U(8.W) // 16,2
// def CSR_CONFIG3_ADDR = "b10000_011".U(8.W) // 16,3
// def CSR_CONFIG4_ADDR = "b10000_100".U(8.W) // 16,4 (sel保留 6or7)
// def CSR_LOAD_LINKED_ADDR = "b10001_000".U(8.W) // 17,0
def CSR_TAGLO_ADDR = "b11100_000".U(8.W) // 28,0
def CSR_TAGHI_ADDR = "b11101_000".U(8.W) // 29,0
def CSR_ERROR_EPC_ADDR = "b11110_000".U(8.W) // 30,0
val CSR_INDEX_ADDR = "b00000_000".U(8.W) // 0,0
val CSR_RANDOM_ADDR = "b00001_000".U(8.W) // 1,0
val CSR_ENTRYLO0_ADDR = "b00010_000".U(8.W) // 2,0
val CSR_ENTRYLO1_ADDR = "b00011_000".U(8.W) // 3,0
val CSR_CONTEXT_ADDR = "b00100_000".U(8.W) // 4,0
// val CSR_CONTEXT_CONFIG_ADDR = "b00100_001".U(8.W) // 4,1
// val CSR_USER_LOCAL_ADDR = "b00100_010".U(8.W) // 4,2
val CSR_PAGE_MASK_ADDR = "b00101_000".U(8.W) // 5,0
// val CSR_PAGE_GRAIN_ADDR = "b00101_001".U(8.W) // 5,1
val CSR_WIRED_ADDR = "b00110_000".U(8.W) // 6,0
// val CSR_HWRENA_ADDR = "b00111_000".U(8.W) // 7,0
val CSR_BADV_ADDR = "b01000_000".U(8.W) // 8,0
val CSR_COUNT_ADDR = "b01001_000".U(8.W) // 9,0 (sel保留 6or7)
val CSR_ENTRYHI_ADDR = "b01010_000".U(8.W) // 10,0
val CSR_COMPARE_ADDR = "b01011_000".U(8.W) // 11,0 (sel保留 6or7)
val CSR_STATUS_ADDR = "b01100_000".U(8.W) // 12,0
// val CSR_INTCTL_ADDR = "b01100_001".U(8.W) // 12,1
// val CSR_SRSCTL_ADDR = "b01100_010".U(8.W) // 12,2
// val CSR_SRSMAP_ADDR = "b01100_011".U(8.W) // 12,3
val CSR_CAUSE_ADDR = "b01101_000".U(8.W) // 13,0
val CSR_EPC_ADDR = "b01110_000".U(8.W) // 14,0
val CSR_PRID_ADDR = "b01111_000".U(8.W) // 15,0
val CSR_EBASE_ADDR = "b01111_001".U(8.W) // 15,1
// val CSR_CDMMBASE_ADDR = "b01111_010".U(8.W) // 15,2
// val CSR_CMGCRBASE_ADDR = "b01111_011".U(8.W) // 15,3
val CSR_CONFIG_ADDR = "b10000_000".U(8.W) // 16,0
val CSR_CONFIG1_ADDR = "b10000_001".U(8.W) // 16,1
// val CSR_CONFIG2_ADDR = "b10000_010".U(8.W) // 16,2
// val CSR_CONFIG3_ADDR = "b10000_011".U(8.W) // 16,3
// val CSR_CONFIG4_ADDR = "b10000_100".U(8.W) // 16,4 (sel保留 6or7)
// val CSR_LOAD_LINKED_ADDR = "b10001_000".U(8.W) // 17,0
val CSR_TAGLO_ADDR = "b11100_000".U(8.W) // 28,0
val CSR_TAGHI_ADDR = "b11101_000".U(8.W) // 29,0
val CSR_ERROR_EPC_ADDR = "b11110_000".U(8.W) // 30,0
def CSR_ADDR_WID = 8
val CSR_ADDR_WID = 8
def PTEBASE_WID = 9
val PTEBASE_WID = 9
}
trait AXIConst {
// AXI
def BURST_FIXED = 0
def BURST_INCR = 1
def BURST_WRAP = 2
def BURST_RESERVED = 3
val BURST_FIXED = 0
val BURST_INCR = 1
val BURST_WRAP = 2
val BURST_RESERVED = 3
def RESP_OKEY = 0
def RESP_EXOKEY = 1
def RESP_SLVERR = 2
def RESP_DECERR = 3
val RESP_OKEY = 0
val RESP_EXOKEY = 1
val RESP_SLVERR = 2
val RESP_DECERR = 3
}
object Const extends Constants with AXIConst with HasExceptionNO

11
chisel/playground/src/defines/Util.scala
View File

@ -36,13 +36,10 @@ object Util {
else s
}
def signedExtend(raw: UInt, to: Int = 32): UInt = {
signedExtend(raw, raw.getWidth, to)
}
def signedExtend(raw: UInt, from: Int, to: Int): UInt = {
require(to > from && from >= 1)
Cat(Fill(to - from, raw(from - 1)), raw)
def signedExtend(a: UInt, len: Int) = {
val aLen = a.getWidth
val signBit = a(aLen - 1)
if (aLen >= len) a(len - 1, 0) else Cat(Fill(len - aLen, signBit), a)
}
def zeroExtend(raw: UInt, to: Int = 32): UInt = {

35
chisel/playground/src/pipeline/decoder/DecoderUnit.scala
View File

@ -60,24 +60,33 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
val ctrl = new DecoderUnitCtrl()
})
if (config.decoderNum == 2) {
val issue = Module(new Issue()).io
issue.allow_to_go := io.ctrl.allow_to_go
issue.instFifo := io.instFifo.info
io.instFifo.allow_to_go(1) := issue.inst1.allow_to_go
for (i <- 0 until (config.decoderNum)) {
decoder(i).io.in.inst := inst(i)
issue.decodeInst(i) := inst_info(i)
issue.execute(i).mem_wreg := io.forward(i).mem_wreg
issue.execute(i).reg_waddr := io.forward(i).exe.waddr
}
io.executeStage.inst1.allow_to_go := issue.inst1.allow_to_go
}
val decoder = Seq.fill(config.decoderNum)(Module(new Decoder()))
val jumpCtrl = Module(new JumpCtrl()).io
val forwardCtrl = Module(new ForwardCtrl()).io
io.regfile(0).src1.raddr := decoder(0).io.out.inst_info.reg1_raddr
io.regfile(0).src2.raddr := decoder(0).io.out.inst_info.reg2_raddr
if (config.decoderNum == 2) {
io.regfile(1).src1.raddr := decoder(1).io.out.inst_info.reg1_raddr
io.regfile(1).src2.raddr := decoder(1).io.out.inst_info.reg2_raddr
}
forwardCtrl.in.forward := io.forward
forwardCtrl.in.regfile := io.regfile // TODO:这里的连接可能有问题
issue.allow_to_go := io.ctrl.allow_to_go
issue.instFifo := io.instFifo.info
jumpCtrl.in.allow_to_go := io.ctrl.allow_to_go
jumpCtrl.in.decoded_inst0 := decoder(0).io.out
jumpCtrl.in.decoded_inst0 := decoder(0).io.out.inst_info
jumpCtrl.in.forward := io.forward
jumpCtrl.in.pc := io.instFifo.inst(0).pc
jumpCtrl.in.reg1_data := io.regfile(0).src1.rdata
@ -88,11 +97,9 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.fetchUnit.target := Mux(io.bpu.pred_branch, io.bpu.branch_target, jumpCtrl.out.jump_target)
io.instFifo.allow_to_go(0) := io.ctrl.allow_to_go
io.instFifo.allow_to_go(1) := issue.inst1.allow_to_go
io.bpu.id_allow_to_go := io.ctrl.allow_to_go
io.bpu.pc := io.instFifo.inst(0).pc
io.bpu.decoded_inst0 := decoder(0).io.out
io.bpu.decoded_inst0 := decoder(0).io.out.inst_info
io.bpu.pht_index := io.instFifo.inst(0).pht_index
io.ctrl.inst0.src1.ren := decoder(0).io.out.inst_info.reg1_ren
@ -107,9 +114,6 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
for (i <- 0 until (config.decoderNum)) {
decoder(i).io.in.inst := inst(i)
issue.decodeInst(i) := inst_info(i)
issue.execute(i).mem_wreg := io.forward(i).mem_wreg
issue.execute(i).reg_waddr := io.forward(i).exe.waddr
}
val int = WireInit(0.U(INT_WID.W))
@ -139,8 +143,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst0.jb_info.pred_branch := io.bpu.pred_branch
io.executeStage.inst0.jb_info.branch_target := io.bpu.branch_target
io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index
io.executeStage.inst1.allow_to_go := issue.inst1.allow_to_go
if (config.decoderNum == 2) {
io.executeStage.inst1.pc := pc(1)
io.executeStage.inst1.inst_info := inst_info(1)
io.executeStage.inst1.src_info.src1_data := Mux(
@ -156,4 +159,8 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst1.ex.excode.map(_ := false.B)
io.executeStage.inst1.ex.excode(illegalInstr) := !decoder(1).io.out.inst_info.inst_valid &&
!hasInt && !io.instFifo.info.almost_empty
}
else {
io.executeStage.inst1 := DontCare
}
}

4
chisel/playground/src/pipeline/decoder/Issue.scala
View File

@ -23,6 +23,7 @@ class Issue(implicit val config: CpuConfig) extends Module {
})
})
if (config.decoderNum == 2) {
val inst0 = io.decodeInst(0)
val inst1 = io.decodeInst(1)
@ -54,4 +55,7 @@ class Issue(implicit val config: CpuConfig) extends Module {
!struct_conflict &&
!data_conflict &&
!VecInit(FuType.bru, FuType.mou).contains(io.decodeInst(1).fusel)
} else {
io.inst1.allow_to_go := false.B
}
}

7
chisel/playground/src/pipeline/decoder/JumpCtrl.scala
View File

@ -29,11 +29,18 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module {
val jump_register_inst = VecInit(ALUOpType.jalr).contains(op)
io.out.jump_inst := jump_inst || jump_register_inst
io.out.jump := io.in.allow_to_go && (jump_inst || jump_register_inst && !io.out.jump_register)
if (config.decoderNum == 2) {
io.out.jump_register := jump_register_inst &&
((io.in.forward(0).exe.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).exe.waddr) ||
(io.in.forward(1).exe.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(1).exe.waddr) ||
(io.in.forward(0).mem.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).mem.waddr) ||
(io.in.forward(1).mem.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(1).mem.waddr))
} else {
io.out.jump_register := jump_register_inst &&
((io.in.forward(0).exe.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).exe.waddr) ||
(io.in.forward(0).mem.wen && io.in.decoded_inst0.reg1_raddr === io.in.forward(0).mem.waddr))
}
val pc_plus_4 = io.in.pc + 4.U(PC_WID.W)
io.out.jump_target := Mux(
jump_inst,

2
chisel/playground/src/pipeline/execute/ExecuteStage.scala
View File

@ -4,7 +4,7 @@ import chisel3._
import chisel3.util._
import cpu.defines._
import cpu.defines.Const._
import cpu.{CpuConfig, BranchPredictorConfig}
import cpu.{BranchPredictorConfig, CpuConfig}
class IdExeInst0 extends Bundle {
val config = new BranchPredictorConfig()

3
chisel/playground/test/src/TestMain.scala
View File

@ -2,10 +2,11 @@ import cpu._
import circt.stage._
import cache.Cache
import cpu.pipeline.decoder.Decoder
import cpu.pipeline.decoder.DecoderUnit
object TestMain extends App {
implicit val config = new CpuConfig()
def top = new Decoder()
def top = new DecoderUnit()
val useMFC = false // use MLIR-based firrtl compiler
val generator = Seq(chisel3.stage.ChiselGeneratorAnnotation(() => top))
if (useMFC) {