refactor: 美化代码
This commit is contained in:
Liphen
parent
de26a56cc2
commit
7df36c2c38
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@ -1 +1 @@
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Subproject commit 219f3b97c692c2b0c16aca7769487e3ab4fbe0a5
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Subproject commit 4e7d97f7753774b966e5dcacfc9a2e6704d4e4d9
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@ -56,19 +56,8 @@ class Core(implicit val config: CpuConfig) extends Module {
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io.inst.addr(i) := fetchUnit.iCache.pc_next + ((i - 1) * 4).U
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}
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bpu.decoder.ena := ctrl.decoderUnit.allow_to_go
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bpu.decoder.op := decoderUnit.bpu.decoded_inst0.op
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bpu.decoder.fusel := decoderUnit.bpu.decoded_inst0.fusel
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bpu.decoder.inst := decoderUnit.bpu.decoded_inst0.inst
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bpu.decoder.rs1 := decoderUnit.bpu.decoded_inst0.reg1_raddr
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bpu.decoder.rs2 := decoderUnit.bpu.decoded_inst0.reg2_raddr
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bpu.decoder.pc := decoderUnit.bpu.pc
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bpu.decoder.pht_index := decoderUnit.bpu.pht_index
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decoderUnit.bpu.update_pht_index := bpu.decoder.update_pht_index
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bpu.decoder <> decoderUnit.bpu
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bpu.execute <> executeUnit.bpu
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decoderUnit.bpu.branch_inst := bpu.decoder.branch_inst
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decoderUnit.bpu.pred_branch := bpu.decoder.pred_branch
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decoderUnit.bpu.branch_target := bpu.decoder.branch_target
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instFifo.do_flush := ctrl.decoderUnit.do_flush
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instFifo.ren <> decoderUnit.instFifo.allow_to_go
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@ -98,9 +87,10 @@ class Core(implicit val config: CpuConfig) extends Module {
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ctrl.executeUnit.do_flush && ctrl.executeUnit.allow_to_go ||
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!ctrl.decoderUnit.allow_to_go && ctrl.executeUnit.allow_to_go
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executeStage.ctrl.clear(1) := ctrl.memoryUnit.flush ||
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(ctrl.executeUnit.do_flush && decoderUnit.executeStage.inst1.allow_to_go) ||
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(ctrl.executeUnit.allow_to_go && !decoderUnit.executeStage.inst1.allow_to_go)
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executeStage.ctrl.inst0_allow_to_go := ctrl.executeUnit.allow_to_go
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(ctrl.executeUnit.do_flush && decoderUnit.instFifo.allow_to_go(1)) ||
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(ctrl.executeUnit.allow_to_go && !decoderUnit.instFifo.allow_to_go(1))
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executeStage.ctrl.allow_to_go(0) := ctrl.executeUnit.allow_to_go
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executeStage.ctrl.allow_to_go(1) := decoderUnit.instFifo.allow_to_go(1)
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executeUnit.executeStage <> executeStage.executeUnit
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executeUnit.csr <> csr.executeUnit
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@ -25,6 +25,18 @@ class DataForwardToDecoderUnit extends Bundle {
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val mem = new RegWrite()
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}
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class DecoderBranchPredictorUnit extends Bundle {
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val bpuConfig = new BranchPredictorConfig()
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val pc = Output(UInt(PC_WID.W))
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val info = Output(new InstInfo())
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val pht_index = Output(UInt(bpuConfig.phtDepth.W))
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val branch_inst = Input(Bool())
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val pred_branch = Input(Bool())
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val branch_target = Input(UInt(PC_WID.W))
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val update_pht_index = Input(UInt(bpuConfig.phtDepth.W))
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}
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class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExceptionNO with HasCSRConst {
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val io = IO(new Bundle {
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// 输入
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@ -37,18 +49,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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val branch = Output(Bool())
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val target = Output(UInt(PC_WID.W))
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}
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val bpu = new Bundle {
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val bpuConfig = new BranchPredictorConfig()
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val pc = Output(UInt(PC_WID.W))
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val decoded_inst0 = Output(new InstInfo())
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val id_allow_to_go = Output(Bool())
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val pht_index = Output(UInt(bpuConfig.phtDepth.W))
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val branch_inst = Input(Bool())
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val pred_branch = Input(Bool())
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val branch_target = Input(UInt(PC_WID.W))
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val update_pht_index = Input(UInt(bpuConfig.phtDepth.W))
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}
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val bpu = new DecoderBranchPredictorUnit()
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val executeStage = Output(new DecoderUnitExecuteUnit())
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val ctrl = new DecoderUnitCtrl()
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})
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@ -60,9 +61,13 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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val pc = io.instFifo.inst.map(_.pc)
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val inst = io.instFifo.inst.map(_.inst)
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val info = decoder.map(_.io.out.info)
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val info = Wire(Vec(config.decoderNum, new InstInfo()))
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val mode = io.csr.mode
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info := decoder.map(_.io.out.info)
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info(0).valid := !io.instFifo.info.empty
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info(1).valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty
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issue.allow_to_go := io.ctrl.allow_to_go
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issue.instFifo := io.instFifo.info
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io.instFifo.allow_to_go(1) := issue.inst1.allow_to_go
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@ -72,40 +77,36 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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issue.execute(i).mem_wreg := io.forward(i).mem_wreg
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issue.execute(i).reg_waddr := io.forward(i).exe.waddr
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}
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io.executeStage.inst1.allow_to_go := issue.inst1.allow_to_go
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io.regfile(0).src1.raddr := decoder(0).io.out.info.reg1_raddr
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io.regfile(0).src2.raddr := decoder(0).io.out.info.reg2_raddr
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io.regfile(1).src1.raddr := decoder(1).io.out.info.reg1_raddr
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io.regfile(1).src2.raddr := decoder(1).io.out.info.reg2_raddr
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io.regfile(0).src1.raddr := info(0).reg1_raddr
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io.regfile(0).src2.raddr := info(0).reg2_raddr
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io.regfile(1).src1.raddr := info(1).reg1_raddr
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io.regfile(1).src2.raddr := info(1).reg2_raddr
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forwardCtrl.in.forward := io.forward
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forwardCtrl.in.regfile := io.regfile // TODO:这里的连接可能有问题
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jumpCtrl.in.allow_to_go := io.ctrl.allow_to_go
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jumpCtrl.in.info := decoder(0).io.out.info
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jumpCtrl.in.info := info(0)
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jumpCtrl.in.forward := io.forward
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jumpCtrl.in.pc := io.instFifo.inst(0).pc
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jumpCtrl.in.src_info := io.executeStage.inst0.src_info
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val inst0_branch = jumpCtrl.out.jump || io.bpu.pred_branch
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io.fetchUnit.branch := inst0_branch
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io.fetchUnit.branch := inst0_branch && io.ctrl.allow_to_go
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io.fetchUnit.target := Mux(io.bpu.pred_branch, io.bpu.branch_target, jumpCtrl.out.jump_target)
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io.instFifo.allow_to_go(0) := io.ctrl.allow_to_go
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io.bpu.id_allow_to_go := io.ctrl.allow_to_go
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io.bpu.pc := io.instFifo.inst(0).pc
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io.bpu.decoded_inst0 := decoder(0).io.out.info
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io.bpu.info := info(0)
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io.bpu.pht_index := io.instFifo.inst(0).pht_index
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io.ctrl.inst0.src1.ren := decoder(0).io.out.info.reg1_ren
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io.ctrl.inst0.src1.raddr := decoder(0).io.out.info.reg1_raddr
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io.ctrl.inst0.src2.ren := decoder(0).io.out.info.reg2_ren
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io.ctrl.inst0.src2.raddr := decoder(0).io.out.info.reg2_raddr
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io.ctrl.branch := inst0_branch
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io.ctrl.inst0.src1.ren := info(0).reg1_ren
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io.ctrl.inst0.src1.raddr := info(0).reg1_raddr
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io.ctrl.inst0.src2.ren := info(0).reg2_ren
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io.ctrl.inst0.src2.raddr := info(0).reg2_raddr
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io.ctrl.branch := io.fetchUnit.branch
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io.executeStage.inst0.pc := pc(0)
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io.executeStage.inst0.info := info(0)
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io.executeStage.inst0.info.valid := !io.instFifo.info.empty
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io.executeStage.inst0.pc := pc(0)
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io.executeStage.inst0.info := info(0)
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io.executeStage.inst0.src_info.src1_data := MuxCase(
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SignedExtend(pc(0), INST_ADDR_WID),
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Seq(
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@ -116,7 +117,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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io.executeStage.inst0.src_info.src2_data := Mux(
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info(0).reg2_ren,
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forwardCtrl.out.inst(0).src2.rdata,
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decoder(0).io.out.info.imm
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info(0).imm
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)
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(0 until (INT_WID)).foreach(i => io.executeStage.inst0.ex.interrupt(i) := io.csr.interrupt(i))
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io.executeStage.inst0.ex.exception.map(_ := false.B)
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@ -146,9 +147,8 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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io.executeStage.inst0.jb_info.branch_target := io.bpu.branch_target
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io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index
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io.executeStage.inst1.pc := pc(1)
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io.executeStage.inst1.info := info(1)
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io.executeStage.inst1.info.valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty
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io.executeStage.inst1.pc := pc(1)
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io.executeStage.inst1.info := info(1)
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io.executeStage.inst1.src_info.src1_data := MuxCase(
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SignedExtend(pc(1), INST_ADDR_WID),
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Seq(
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@ -159,7 +159,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
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io.executeStage.inst1.src_info.src2_data := Mux(
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info(1).reg2_ren,
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forwardCtrl.out.inst(1).src2.rdata,
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decoder(1).io.out.info.imm
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info(1).imm
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)
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(0 until (INT_WID)).foreach(i => io.executeStage.inst1.ex.interrupt(i) := io.csr.interrupt(i))
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io.executeStage.inst1.ex.exception.map(_ := false.B)
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@ -10,11 +10,10 @@ import cpu.CpuConfig
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class JumpCtrl(implicit val config: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val in = Input(new Bundle {
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val allow_to_go = Bool()
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val pc = UInt(PC_WID.W)
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val info = new InstInfo()
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val src_info = new SrcInfo()
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val forward = Vec(config.fuNum, new DataForwardToDecoderUnit())
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val pc = UInt(PC_WID.W)
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val info = new InstInfo()
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val src_info = new SrcInfo()
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val forward = Vec(config.fuNum, new DataForwardToDecoderUnit())
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})
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val out = Output(new Bundle {
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val jump_inst = Bool()
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@ -24,20 +23,22 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module {
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})
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})
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val valid = io.in.info.valid
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val op = io.in.info.op
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val jump_inst = VecInit(ALUOpType.jal).contains(op)
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val jump_register_inst = VecInit(ALUOpType.jalr).contains(op)
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val fusel = io.in.info.fusel
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val jump_inst = VecInit(ALUOpType.jal).contains(op) && fusel === FuType.bru
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val jump_register_inst = VecInit(ALUOpType.jalr).contains(op) && fusel === FuType.bru
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io.out.jump_inst := jump_inst || jump_register_inst
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io.out.jump := io.in.allow_to_go && (jump_inst || jump_register_inst && !io.out.jump_register)
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io.out.jump := (jump_inst || jump_register_inst && !io.out.jump_register) && valid
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if (config.decoderNum == 2) {
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io.out.jump_register := jump_register_inst &&
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io.out.jump_register := jump_register_inst && io.in.info.reg1_raddr.orR &&
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((io.in.forward(0).exe.wen && io.in.info.reg1_raddr === io.in.forward(0).exe.waddr) ||
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(io.in.forward(1).exe.wen && io.in.info.reg1_raddr === io.in.forward(1).exe.waddr) ||
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(io.in.forward(0).mem.wen && io.in.info.reg1_raddr === io.in.forward(0).mem.waddr) ||
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(io.in.forward(1).mem.wen && io.in.info.reg1_raddr === io.in.forward(1).mem.waddr))
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} else {
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io.out.jump_register := jump_register_inst &&
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io.out.jump_register := jump_register_inst && io.in.info.reg1_raddr.orR &&
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((io.in.forward(0).exe.wen && io.in.info.reg1_raddr === io.in.forward(0).exe.waddr) ||
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(io.in.forward(0).mem.wen && io.in.info.reg1_raddr === io.in.forward(0).mem.waddr))
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}
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@ -24,7 +24,6 @@ class IdExeInst0 extends Bundle {
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}
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class IdExeInst1 extends Bundle {
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val allow_to_go = Bool()
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val pc = UInt(PC_WID.W)
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val info = new InstInfo()
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val src_info = new SrcInfo()
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@ -39,7 +38,7 @@ class DecoderUnitExecuteUnit extends Bundle {
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class ExecuteStage(implicit val config: CpuConfig) extends Module {
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val io = IO(new Bundle {
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val ctrl = Input(new Bundle {
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val inst0_allow_to_go = Bool()
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val allow_to_go = Vec(config.decoderNum,Bool())
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val clear = Vec(config.decoderNum, Bool())
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})
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val decoderUnit = Input(new DecoderUnitExecuteUnit())
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@ -51,13 +50,13 @@ class ExecuteStage(implicit val config: CpuConfig) extends Module {
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when(io.ctrl.clear(0)) {
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inst0 := 0.U.asTypeOf(new IdExeInst0())
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}.elsewhen(io.ctrl.inst0_allow_to_go) {
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}.elsewhen(io.ctrl.allow_to_go(0)) {
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inst0 := io.decoderUnit.inst0
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}
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when(io.ctrl.clear(1)) {
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inst1 := 0.U.asTypeOf(new IdExeInst1())
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}.elsewhen(io.decoderUnit.inst1.allow_to_go) {
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}.elsewhen(io.ctrl.allow_to_go(1)) {
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inst1 := io.decoderUnit.inst1
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}
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@ -9,6 +9,7 @@ import cpu.defines.ALUOpType
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import cpu.defines.FuOpType
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import cpu.defines.FuType
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import cpu.defines.SignedExtend
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import cpu.pipeline.decoder.DecoderBranchPredictorUnit
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class ExecuteUnitBranchPredictor extends Bundle {
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val bpuConfig = new BranchPredictorConfig()
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@ -20,22 +21,7 @@ class ExecuteUnitBranchPredictor extends Bundle {
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class BranchPredictorIO(implicit config: CpuConfig) extends Bundle {
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val bpuConfig = new BranchPredictorConfig()
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val decoder = new Bundle {
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val inst = Input(UInt(INST_WID.W))
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val op = Input(FuOpType())
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val fusel = Input(FuType())
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val ena = Input(Bool())
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val pc = Input(UInt(PC_WID.W))
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val pht_index = Input(UInt(bpuConfig.phtDepth.W))
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val rs1 = Input(UInt(REG_ADDR_WID.W))
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val rs2 = Input(UInt(REG_ADDR_WID.W))
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val branch_inst = Output(Bool())
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val pred_branch = Output(Bool())
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val branch_target = Output(UInt(PC_WID.W))
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val update_pht_index = Output(UInt(bpuConfig.phtDepth.W))
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}
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val decoder = Flipped(new DecoderBranchPredictorUnit())
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val instBuffer = new Bundle {
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val pc = Input(Vec(config.instFetchNum, UInt(PC_WID.W)))
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@ -72,10 +58,10 @@ class GlobalBranchPredictor(
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val strongly_not_taken :: weakly_not_taken :: weakly_taken :: strongly_taken :: Nil = Enum(4)
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val inst = io.decoder.inst
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val imm = SignedExtend(Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)), XLEN)
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val imm = io.decoder.info.imm
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io.decoder.branch_inst := FuType.bru === io.decoder.fusel && ALUOpType.isBranch(io.decoder.op)
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io.decoder.branch_inst := io.decoder.info.valid &&
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FuType.bru === io.decoder.info.fusel && ALUOpType.isBranch(io.decoder.info.op)
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io.decoder.branch_target := io.decoder.pc + imm
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// 局部预测模式
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@ -85,7 +71,7 @@ class GlobalBranchPredictor(
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val pht_index = bht(bht_index)
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io.decoder.pred_branch :=
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io.decoder.ena && io.decoder.branch_inst && (pht(pht_index) === weakly_taken || pht(pht_index) === strongly_taken)
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io.decoder.branch_inst && (pht(pht_index) === weakly_taken || pht(pht_index) === strongly_taken)
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val update_bht_index = io.execute.pc(1 + BHT_DEPTH, 2)
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val update_pht_index = bht(update_bht_index)
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@ -121,10 +107,10 @@ class AdaptiveTwoLevelPredictor(
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val strongly_not_taken :: weakly_not_taken :: weakly_taken :: strongly_taken :: Nil = Enum(4)
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val inst = io.decoder.inst
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val imm = SignedExtend(Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)), XLEN)
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val imm = io.decoder.info.imm
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io.decoder.branch_inst := FuType.bru === io.decoder.fusel && ALUOpType.isBranch(io.decoder.op)
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io.decoder.branch_inst := io.decoder.info.valid &&
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FuType.bru === io.decoder.info.fusel && ALUOpType.isBranch(io.decoder.info.op)
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io.decoder.branch_target := io.decoder.pc + imm
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val bht = RegInit(VecInit(Seq.fill(1 << BHT_DEPTH)(0.U(PHT_DEPTH.W))))
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@ -136,7 +122,7 @@ class AdaptiveTwoLevelPredictor(
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}
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io.decoder.pred_branch :=
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io.decoder.ena && io.decoder.branch_inst && (pht(pht_index) === weakly_taken || pht(pht_index) === strongly_taken)
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io.decoder.branch_inst && (pht(pht_index) === weakly_taken || pht(pht_index) === strongly_taken)
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io.decoder.update_pht_index := bht(io.decoder.pc(1 + BHT_DEPTH, 2))
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val update_bht_index = io.execute.pc(1 + BHT_DEPTH, 2)
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