From 7df36c2c383e82eabeedecefccfe6e24f86254c2 Mon Sep 17 00:00:00 2001 From: Liphen Date: Mon, 11 Dec 2023 15:04:58 +0800 Subject: [PATCH] =?UTF-8?q?refactor:=20=E7=BE=8E=E5=8C=96=E4=BB=A3?= =?UTF-8?q?=E7=A0=81?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/difftest | 2 +- chisel/playground/src/Core.scala | 20 ++---- .../src/pipeline/decoder/DecoderUnit.scala | 72 +++++++++---------- .../src/pipeline/decoder/JumpCtrl.scala | 21 +++--- .../src/pipeline/execute/ExecuteStage.scala | 7 +- .../pipeline/fetch/BranchPredictorUnit.scala | 34 +++------ 6 files changed, 66 insertions(+), 90 deletions(-) diff --git a/chisel/difftest b/chisel/difftest index 219f3b9..4e7d97f 160000 --- a/chisel/difftest +++ b/chisel/difftest @@ -1 +1 @@ -Subproject commit 219f3b97c692c2b0c16aca7769487e3ab4fbe0a5 +Subproject commit 4e7d97f7753774b966e5dcacfc9a2e6704d4e4d9 diff --git a/chisel/playground/src/Core.scala b/chisel/playground/src/Core.scala index adecd63..06178b6 100644 --- a/chisel/playground/src/Core.scala +++ b/chisel/playground/src/Core.scala @@ -56,19 +56,8 @@ class Core(implicit val config: CpuConfig) extends Module { io.inst.addr(i) := fetchUnit.iCache.pc_next + ((i - 1) * 4).U } - bpu.decoder.ena := ctrl.decoderUnit.allow_to_go - bpu.decoder.op := decoderUnit.bpu.decoded_inst0.op - bpu.decoder.fusel := decoderUnit.bpu.decoded_inst0.fusel - bpu.decoder.inst := decoderUnit.bpu.decoded_inst0.inst - bpu.decoder.rs1 := decoderUnit.bpu.decoded_inst0.reg1_raddr - bpu.decoder.rs2 := decoderUnit.bpu.decoded_inst0.reg2_raddr - bpu.decoder.pc := decoderUnit.bpu.pc - bpu.decoder.pht_index := decoderUnit.bpu.pht_index - decoderUnit.bpu.update_pht_index := bpu.decoder.update_pht_index + bpu.decoder <> decoderUnit.bpu bpu.execute <> executeUnit.bpu - decoderUnit.bpu.branch_inst := bpu.decoder.branch_inst - decoderUnit.bpu.pred_branch := bpu.decoder.pred_branch - decoderUnit.bpu.branch_target := bpu.decoder.branch_target instFifo.do_flush := ctrl.decoderUnit.do_flush instFifo.ren <> decoderUnit.instFifo.allow_to_go @@ -98,9 +87,10 @@ class Core(implicit val config: CpuConfig) extends Module { ctrl.executeUnit.do_flush && ctrl.executeUnit.allow_to_go || !ctrl.decoderUnit.allow_to_go && ctrl.executeUnit.allow_to_go executeStage.ctrl.clear(1) := ctrl.memoryUnit.flush || - (ctrl.executeUnit.do_flush && decoderUnit.executeStage.inst1.allow_to_go) || - (ctrl.executeUnit.allow_to_go && !decoderUnit.executeStage.inst1.allow_to_go) - executeStage.ctrl.inst0_allow_to_go := ctrl.executeUnit.allow_to_go + (ctrl.executeUnit.do_flush && decoderUnit.instFifo.allow_to_go(1)) || + (ctrl.executeUnit.allow_to_go && !decoderUnit.instFifo.allow_to_go(1)) + executeStage.ctrl.allow_to_go(0) := ctrl.executeUnit.allow_to_go + executeStage.ctrl.allow_to_go(1) := decoderUnit.instFifo.allow_to_go(1) executeUnit.executeStage <> executeStage.executeUnit executeUnit.csr <> csr.executeUnit diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala index d074ee2..80fab7d 100644 --- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala +++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala @@ -25,6 +25,18 @@ class DataForwardToDecoderUnit extends Bundle { val mem = new RegWrite() } +class DecoderBranchPredictorUnit extends Bundle { + val bpuConfig = new BranchPredictorConfig() + val pc = Output(UInt(PC_WID.W)) + val info = Output(new InstInfo()) + val pht_index = Output(UInt(bpuConfig.phtDepth.W)) + + val branch_inst = Input(Bool()) + val pred_branch = Input(Bool()) + val branch_target = Input(UInt(PC_WID.W)) + val update_pht_index = Input(UInt(bpuConfig.phtDepth.W)) +} + class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExceptionNO with HasCSRConst { val io = IO(new Bundle { // 输入 @@ -37,18 +49,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti val branch = Output(Bool()) val target = Output(UInt(PC_WID.W)) } - val bpu = new Bundle { - val bpuConfig = new BranchPredictorConfig() - val pc = Output(UInt(PC_WID.W)) - val decoded_inst0 = Output(new InstInfo()) - val id_allow_to_go = Output(Bool()) - val pht_index = Output(UInt(bpuConfig.phtDepth.W)) - - val branch_inst = Input(Bool()) - val pred_branch = Input(Bool()) - val branch_target = Input(UInt(PC_WID.W)) - val update_pht_index = Input(UInt(bpuConfig.phtDepth.W)) - } + val bpu = new DecoderBranchPredictorUnit() val executeStage = Output(new DecoderUnitExecuteUnit()) val ctrl = new DecoderUnitCtrl() }) @@ -60,9 +61,13 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti val pc = io.instFifo.inst.map(_.pc) val inst = io.instFifo.inst.map(_.inst) - val info = decoder.map(_.io.out.info) + val info = Wire(Vec(config.decoderNum, new InstInfo())) val mode = io.csr.mode + info := decoder.map(_.io.out.info) + info(0).valid := !io.instFifo.info.empty + info(1).valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty + issue.allow_to_go := io.ctrl.allow_to_go issue.instFifo := io.instFifo.info io.instFifo.allow_to_go(1) := issue.inst1.allow_to_go @@ -72,40 +77,36 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti issue.execute(i).mem_wreg := io.forward(i).mem_wreg issue.execute(i).reg_waddr := io.forward(i).exe.waddr } - io.executeStage.inst1.allow_to_go := issue.inst1.allow_to_go - io.regfile(0).src1.raddr := decoder(0).io.out.info.reg1_raddr - io.regfile(0).src2.raddr := decoder(0).io.out.info.reg2_raddr - io.regfile(1).src1.raddr := decoder(1).io.out.info.reg1_raddr - io.regfile(1).src2.raddr := decoder(1).io.out.info.reg2_raddr + io.regfile(0).src1.raddr := info(0).reg1_raddr + io.regfile(0).src2.raddr := info(0).reg2_raddr + io.regfile(1).src1.raddr := info(1).reg1_raddr + io.regfile(1).src2.raddr := info(1).reg2_raddr forwardCtrl.in.forward := io.forward forwardCtrl.in.regfile := io.regfile // TODO:这里的连接可能有问题 - jumpCtrl.in.allow_to_go := io.ctrl.allow_to_go - jumpCtrl.in.info := decoder(0).io.out.info + jumpCtrl.in.info := info(0) jumpCtrl.in.forward := io.forward jumpCtrl.in.pc := io.instFifo.inst(0).pc jumpCtrl.in.src_info := io.executeStage.inst0.src_info val inst0_branch = jumpCtrl.out.jump || io.bpu.pred_branch - io.fetchUnit.branch := inst0_branch + io.fetchUnit.branch := inst0_branch && io.ctrl.allow_to_go io.fetchUnit.target := Mux(io.bpu.pred_branch, io.bpu.branch_target, jumpCtrl.out.jump_target) io.instFifo.allow_to_go(0) := io.ctrl.allow_to_go - io.bpu.id_allow_to_go := io.ctrl.allow_to_go io.bpu.pc := io.instFifo.inst(0).pc - io.bpu.decoded_inst0 := decoder(0).io.out.info + io.bpu.info := info(0) io.bpu.pht_index := io.instFifo.inst(0).pht_index - io.ctrl.inst0.src1.ren := decoder(0).io.out.info.reg1_ren - io.ctrl.inst0.src1.raddr := decoder(0).io.out.info.reg1_raddr - io.ctrl.inst0.src2.ren := decoder(0).io.out.info.reg2_ren - io.ctrl.inst0.src2.raddr := decoder(0).io.out.info.reg2_raddr - io.ctrl.branch := inst0_branch + io.ctrl.inst0.src1.ren := info(0).reg1_ren + io.ctrl.inst0.src1.raddr := info(0).reg1_raddr + io.ctrl.inst0.src2.ren := info(0).reg2_ren + io.ctrl.inst0.src2.raddr := info(0).reg2_raddr + io.ctrl.branch := io.fetchUnit.branch - io.executeStage.inst0.pc := pc(0) - io.executeStage.inst0.info := info(0) - io.executeStage.inst0.info.valid := !io.instFifo.info.empty + io.executeStage.inst0.pc := pc(0) + io.executeStage.inst0.info := info(0) io.executeStage.inst0.src_info.src1_data := MuxCase( SignedExtend(pc(0), INST_ADDR_WID), Seq( @@ -116,7 +117,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti io.executeStage.inst0.src_info.src2_data := Mux( info(0).reg2_ren, forwardCtrl.out.inst(0).src2.rdata, - decoder(0).io.out.info.imm + info(0).imm ) (0 until (INT_WID)).foreach(i => io.executeStage.inst0.ex.interrupt(i) := io.csr.interrupt(i)) io.executeStage.inst0.ex.exception.map(_ := false.B) @@ -146,9 +147,8 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti io.executeStage.inst0.jb_info.branch_target := io.bpu.branch_target io.executeStage.inst0.jb_info.update_pht_index := io.bpu.update_pht_index - io.executeStage.inst1.pc := pc(1) - io.executeStage.inst1.info := info(1) - io.executeStage.inst1.info.valid := !io.instFifo.info.almost_empty && !io.instFifo.info.empty + io.executeStage.inst1.pc := pc(1) + io.executeStage.inst1.info := info(1) io.executeStage.inst1.src_info.src1_data := MuxCase( SignedExtend(pc(1), INST_ADDR_WID), Seq( @@ -159,7 +159,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti io.executeStage.inst1.src_info.src2_data := Mux( info(1).reg2_ren, forwardCtrl.out.inst(1).src2.rdata, - decoder(1).io.out.info.imm + info(1).imm ) (0 until (INT_WID)).foreach(i => io.executeStage.inst1.ex.interrupt(i) := io.csr.interrupt(i)) io.executeStage.inst1.ex.exception.map(_ := false.B) diff --git a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala index 7a483e0..98c2583 100644 --- a/chisel/playground/src/pipeline/decoder/JumpCtrl.scala +++ b/chisel/playground/src/pipeline/decoder/JumpCtrl.scala @@ -10,11 +10,10 @@ import cpu.CpuConfig class JumpCtrl(implicit val config: CpuConfig) extends Module { val io = IO(new Bundle { val in = Input(new Bundle { - val allow_to_go = Bool() - val pc = UInt(PC_WID.W) - val info = new InstInfo() - val src_info = new SrcInfo() - val forward = Vec(config.fuNum, new DataForwardToDecoderUnit()) + val pc = UInt(PC_WID.W) + val info = new InstInfo() + val src_info = new SrcInfo() + val forward = Vec(config.fuNum, new DataForwardToDecoderUnit()) }) val out = Output(new Bundle { val jump_inst = Bool() @@ -24,20 +23,22 @@ class JumpCtrl(implicit val config: CpuConfig) extends Module { }) }) + val valid = io.in.info.valid val op = io.in.info.op - val jump_inst = VecInit(ALUOpType.jal).contains(op) - val jump_register_inst = VecInit(ALUOpType.jalr).contains(op) + val fusel = io.in.info.fusel + val jump_inst = VecInit(ALUOpType.jal).contains(op) && fusel === FuType.bru + val jump_register_inst = VecInit(ALUOpType.jalr).contains(op) && fusel === FuType.bru io.out.jump_inst := jump_inst || jump_register_inst - io.out.jump := io.in.allow_to_go && (jump_inst || jump_register_inst && !io.out.jump_register) + io.out.jump := (jump_inst || jump_register_inst && !io.out.jump_register) && valid if (config.decoderNum == 2) { - io.out.jump_register := jump_register_inst && + io.out.jump_register := jump_register_inst && io.in.info.reg1_raddr.orR && ((io.in.forward(0).exe.wen && io.in.info.reg1_raddr === io.in.forward(0).exe.waddr) || (io.in.forward(1).exe.wen && io.in.info.reg1_raddr === io.in.forward(1).exe.waddr) || (io.in.forward(0).mem.wen && io.in.info.reg1_raddr === io.in.forward(0).mem.waddr) || (io.in.forward(1).mem.wen && io.in.info.reg1_raddr === io.in.forward(1).mem.waddr)) } else { - io.out.jump_register := jump_register_inst && + io.out.jump_register := jump_register_inst && io.in.info.reg1_raddr.orR && ((io.in.forward(0).exe.wen && io.in.info.reg1_raddr === io.in.forward(0).exe.waddr) || (io.in.forward(0).mem.wen && io.in.info.reg1_raddr === io.in.forward(0).mem.waddr)) } diff --git a/chisel/playground/src/pipeline/execute/ExecuteStage.scala b/chisel/playground/src/pipeline/execute/ExecuteStage.scala index 269c450..f191597 100644 --- a/chisel/playground/src/pipeline/execute/ExecuteStage.scala +++ b/chisel/playground/src/pipeline/execute/ExecuteStage.scala @@ -24,7 +24,6 @@ class IdExeInst0 extends Bundle { } class IdExeInst1 extends Bundle { - val allow_to_go = Bool() val pc = UInt(PC_WID.W) val info = new InstInfo() val src_info = new SrcInfo() @@ -39,7 +38,7 @@ class DecoderUnitExecuteUnit extends Bundle { class ExecuteStage(implicit val config: CpuConfig) extends Module { val io = IO(new Bundle { val ctrl = Input(new Bundle { - val inst0_allow_to_go = Bool() + val allow_to_go = Vec(config.decoderNum,Bool()) val clear = Vec(config.decoderNum, Bool()) }) val decoderUnit = Input(new DecoderUnitExecuteUnit()) @@ -51,13 +50,13 @@ class ExecuteStage(implicit val config: CpuConfig) extends Module { when(io.ctrl.clear(0)) { inst0 := 0.U.asTypeOf(new IdExeInst0()) - }.elsewhen(io.ctrl.inst0_allow_to_go) { + }.elsewhen(io.ctrl.allow_to_go(0)) { inst0 := io.decoderUnit.inst0 } when(io.ctrl.clear(1)) { inst1 := 0.U.asTypeOf(new IdExeInst1()) - }.elsewhen(io.decoderUnit.inst1.allow_to_go) { + }.elsewhen(io.ctrl.allow_to_go(1)) { inst1 := io.decoderUnit.inst1 } diff --git a/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala b/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala index 8b2943a..6b0be0c 100644 --- a/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala +++ b/chisel/playground/src/pipeline/fetch/BranchPredictorUnit.scala @@ -9,6 +9,7 @@ import cpu.defines.ALUOpType import cpu.defines.FuOpType import cpu.defines.FuType import cpu.defines.SignedExtend +import cpu.pipeline.decoder.DecoderBranchPredictorUnit class ExecuteUnitBranchPredictor extends Bundle { val bpuConfig = new BranchPredictorConfig() @@ -20,22 +21,7 @@ class ExecuteUnitBranchPredictor extends Bundle { class BranchPredictorIO(implicit config: CpuConfig) extends Bundle { val bpuConfig = new BranchPredictorConfig() - val decoder = new Bundle { - val inst = Input(UInt(INST_WID.W)) - val op = Input(FuOpType()) - val fusel = Input(FuType()) - val ena = Input(Bool()) - val pc = Input(UInt(PC_WID.W)) - val pht_index = Input(UInt(bpuConfig.phtDepth.W)) - - val rs1 = Input(UInt(REG_ADDR_WID.W)) - val rs2 = Input(UInt(REG_ADDR_WID.W)) - - val branch_inst = Output(Bool()) - val pred_branch = Output(Bool()) - val branch_target = Output(UInt(PC_WID.W)) - val update_pht_index = Output(UInt(bpuConfig.phtDepth.W)) - } + val decoder = Flipped(new DecoderBranchPredictorUnit()) val instBuffer = new Bundle { val pc = Input(Vec(config.instFetchNum, UInt(PC_WID.W))) @@ -72,10 +58,10 @@ class GlobalBranchPredictor( val strongly_not_taken :: weakly_not_taken :: weakly_taken :: strongly_taken :: Nil = Enum(4) - val inst = io.decoder.inst - val imm = SignedExtend(Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)), XLEN) + val imm = io.decoder.info.imm - io.decoder.branch_inst := FuType.bru === io.decoder.fusel && ALUOpType.isBranch(io.decoder.op) + io.decoder.branch_inst := io.decoder.info.valid && + FuType.bru === io.decoder.info.fusel && ALUOpType.isBranch(io.decoder.info.op) io.decoder.branch_target := io.decoder.pc + imm // 局部预测模式 @@ -85,7 +71,7 @@ class GlobalBranchPredictor( val pht_index = bht(bht_index) io.decoder.pred_branch := - io.decoder.ena && io.decoder.branch_inst && (pht(pht_index) === weakly_taken || pht(pht_index) === strongly_taken) + io.decoder.branch_inst && (pht(pht_index) === weakly_taken || pht(pht_index) === strongly_taken) val update_bht_index = io.execute.pc(1 + BHT_DEPTH, 2) val update_pht_index = bht(update_bht_index) @@ -121,10 +107,10 @@ class AdaptiveTwoLevelPredictor( val strongly_not_taken :: weakly_not_taken :: weakly_taken :: strongly_taken :: Nil = Enum(4) - val inst = io.decoder.inst - val imm = SignedExtend(Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)), XLEN) + val imm = io.decoder.info.imm - io.decoder.branch_inst := FuType.bru === io.decoder.fusel && ALUOpType.isBranch(io.decoder.op) + io.decoder.branch_inst := io.decoder.info.valid && + FuType.bru === io.decoder.info.fusel && ALUOpType.isBranch(io.decoder.info.op) io.decoder.branch_target := io.decoder.pc + imm val bht = RegInit(VecInit(Seq.fill(1 << BHT_DEPTH)(0.U(PHT_DEPTH.W)))) @@ -136,7 +122,7 @@ class AdaptiveTwoLevelPredictor( } io.decoder.pred_branch := - io.decoder.ena && io.decoder.branch_inst && (pht(pht_index) === weakly_taken || pht(pht_index) === strongly_taken) + io.decoder.branch_inst && (pht(pht_index) === weakly_taken || pht(pht_index) === strongly_taken) io.decoder.update_pht_index := bht(io.decoder.pc(1 + BHT_DEPTH, 2)) val update_bht_index = io.execute.pc(1 + BHT_DEPTH, 2)