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fix(cache): sv39高位需要一致

This commit is contained in:
Liphen 2024-01-17 15:30:25 +08:00
parent 39d5e8e043
commit 7d795f6d80
3 changed files with 16 additions and 5 deletions
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7
chisel/playground/src/cache/DCache.scala vendored
View File

@ -282,7 +282,12 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
val access_fault = RegInit(false.B)
val page_fault = RegInit(false.B)
val addr_err = io.cpu.addr(XLEN - 1, VADDR_WID).orR
// sv39的63-39位需要与第38位相同
val addr_err = io.cpu
.addr(XLEN - 1, VADDR_WID)
.asBools
.map(_ =/= io.cpu.addr(VADDR_WID - 1))
.reduce(_ || _)
io.cpu.access_fault := access_fault
io.cpu.page_fault := page_fault

8
chisel/playground/src/cache/ICache.scala vendored
View File

@ -204,7 +204,13 @@ class ICache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
val access_fault = RegInit(false.B)
val page_fault = RegInit(false.B)
val addr_err = io.cpu.addr(use_next_addr)(XLEN - 1, VADDR_WID).orR
// sv39的63-39位需要与第38位相同
val addr_err =
io.cpu
.addr(use_next_addr)(XLEN - 1, VADDR_WID)
.asBools
.map(_ =/= io.cpu.addr(use_next_addr)(VADDR_WID - 1))
.reduce(_ || _)
io.cpu.access_fault := access_fault //TODO：实现cached段中的访存response错误
io.cpu.page_fault := page_fault

6
chisel/playground/src/pipeline/execute/fu/Csr.scala
View File

@ -377,12 +377,12 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
mstatus := mstatusNew.asUInt
}
val ret_target = Wire(UInt(VADDR_WID.W))
val ret_target = Wire(UInt(XLEN.W))
ret_target := DontCare
val trap_target = Wire(UInt(VADDR_WID.W))
val trap_target = Wire(UInt(XLEN.W))
val tvec = Mux(delegS, stvec, mtvec)
trap_target := (tvec(VADDR_WID - 1, 2) << 2) + Mux(
trap_target := (tvec(XLEN - 1, 2) << 2) + Mux(
tvec(0) && raise_interrupt,
(causeNO << 2),
0.U