diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala
index 67515c1..2a49900 100644
--- a/chisel/playground/src/cache/DCache.scala
+++ b/chisel/playground/src/cache/DCache.scala
@@ -282,7 +282,12 @@ class DCache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
 
   val access_fault = RegInit(false.B)
   val page_fault   = RegInit(false.B)
-  val addr_err     = io.cpu.addr(XLEN - 1, VADDR_WID).orR
+  // sv39的63-39位需要与第38位相同
+  val addr_err = io.cpu
+    .addr(XLEN - 1, VADDR_WID)
+    .asBools
+    .map(_ =/= io.cpu.addr(VADDR_WID - 1))
+    .reduce(_ || _)
 
   io.cpu.access_fault := access_fault
   io.cpu.page_fault   := page_fault
diff --git a/chisel/playground/src/cache/ICache.scala b/chisel/playground/src/cache/ICache.scala
index 05e092b..39e8c71 100644
--- a/chisel/playground/src/cache/ICache.scala
+++ b/chisel/playground/src/cache/ICache.scala
@@ -204,7 +204,13 @@ class ICache(cacheConfig: CacheConfig)(implicit cpuConfig: CpuConfig) extends Mo
 
   val access_fault = RegInit(false.B)
   val page_fault   = RegInit(false.B)
-  val addr_err     = io.cpu.addr(use_next_addr)(XLEN - 1, VADDR_WID).orR
+  // sv39的63-39位需要与第38位相同
+  val addr_err =
+    io.cpu
+      .addr(use_next_addr)(XLEN - 1, VADDR_WID)
+      .asBools
+      .map(_ =/= io.cpu.addr(use_next_addr)(VADDR_WID - 1))
+      .reduce(_ || _)
 
   io.cpu.access_fault := access_fault //TODO：实现cached段中的访存response错误
   io.cpu.page_fault   := page_fault
diff --git a/chisel/playground/src/pipeline/execute/fu/Csr.scala b/chisel/playground/src/pipeline/execute/fu/Csr.scala
index 8dfb90c..e90878b 100644
--- a/chisel/playground/src/pipeline/execute/fu/Csr.scala
+++ b/chisel/playground/src/pipeline/execute/fu/Csr.scala
@@ -377,12 +377,12 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
     mstatus := mstatusNew.asUInt
   }
 
-  val ret_target = Wire(UInt(VADDR_WID.W))
+  val ret_target = Wire(UInt(XLEN.W))
   ret_target := DontCare
 
-  val trap_target = Wire(UInt(VADDR_WID.W))
+  val trap_target = Wire(UInt(XLEN.W))
   val tvec        = Mux(delegS, stvec, mtvec)
-  trap_target := (tvec(VADDR_WID - 1, 2) << 2) + Mux(
+  trap_target := (tvec(XLEN - 1, 2) << 2) + Mux(
     tvec(0) && raise_interrupt,
     (causeNO << 2),
     0.U