生成verilog

chisel/Makefile

@@ -1,4 +1,6 @@
 BUILD_DIR = ./build
+DIFF_DIR = ./difftest/core
+DIFF_WORK_DIR = ./difftest/test/test_workbench/sim
 
 export PATH := $(PATH):$(abspath ./utils)
 
@@ -7,6 +9,10 @@ verilog:
 	mkdir -p $(BUILD_DIR)
 	mill -i __.test.runMain Elaborate -td $(BUILD_DIR)
 
+func:
+	# cp $(BUILD_DIR)/PuaCpu.v $(DIFF_DIR)
+	cd $(DIFF_WORK_DIR) && make func
+
 test:
 	@echo "make test"
 	$(MAKE) clean

chisel/playground/resources/mycpu_top.v

@@ -1,106 +0,0 @@
-module mycpu_top (
-    input  [ 5:0]      ext_int,
-    input              aclk,
-    input              aresetn,
-    //axi interface
-
-    //read request
-    output [ 3:0]      arid,
-    output [31:0]      araddr,
-    output [ 7:0]      arlen,
-    output [ 2:0]      arsize,
-    output [ 1:0]      arburst,
-    output [ 1:0]      arlock,
-    output [ 3:0]      arcache,
-    output [ 2:0]      arprot,
-    output             arvalid,
-    input              arready,
-
-    //read response
-    input  [ 3:0]      rid,
-    input  [31:0]      rdata,
-    input  [ 1:0]      rresp,
-    input              rlast,
-    input              rvalid,
-    output             rready,
-
-    //write request
-    output [ 3:0]      awid,
-    output [31:0]      awaddr,
-    output [ 7:0]      awlen,
-    output [ 2:0]      awsize,
-    output [ 1:0]      awburst,
-    output [ 1:0]      awlock,
-    output [ 3:0]      awcache,
-    output [ 2:0]      awprot,
-    output             awvalid,
-    input              awready,
-
-    //write data
-    output [ 3:0]      wid,
-    output [31:0]      wdata,
-    output [ 3:0]      wstrb,
-    output             wlast,
-    output             wvalid,
-    input              wready,
-
-    //write response
-    input  [ 3:0]      bid,
-    input  [ 1:0]      bresp,
-    input              bvalid,
-    output             bready,
-    
-    // trace debug interface
-    output [31:0]      debug_wb_pc,
-    output [ 3:0]      debug_wb_rf_wen,
-    output [ 4:0]      debug_wb_rf_wnum,
-    output [31:0]      debug_wb_rf_wdata
-);
-
-PuaMips puamips(
-  .clock                      (aclk             ),
-  .reset                      (~aresetn         ),
-  .io_ext_int                 (ext_int          ),
-  .io_axi_ar_bits_id          (arid             ),
-  .io_axi_ar_bits_addr        (araddr           ),
-  .io_axi_ar_bits_len         (arlen            ),
-  .io_axi_ar_bits_size        (arsize           ),
-  .io_axi_ar_bits_burst       (arburst          ),
-  .io_axi_ar_bits_lock        (arlock           ),
-  .io_axi_ar_bits_cache       (arcache          ),
-  .io_axi_ar_bits_prot        (arprot           ),
-  .io_axi_ar_valid            (arvalid          ),
-  .io_axi_ar_ready            (arready          ),
-  .io_axi_r_bits_id           (rid              ),
-  .io_axi_r_bits_data         (rdata            ),
-  .io_axi_r_bits_resp         (rresp            ),
-  .io_axi_r_bits_last         (rlast            ),
-  .io_axi_r_valid             (rvalid           ),
-  .io_axi_r_ready             (rready           ),
-  .io_axi_aw_bits_id          (awid             ),
-  .io_axi_aw_bits_addr        (awaddr           ),
-  .io_axi_aw_bits_len         (awlen            ),
-  .io_axi_aw_bits_size        (awsize           ),
-  .io_axi_aw_bits_burst       (awburst          ),
-  .io_axi_aw_bits_lock        (awlock           ),
-  .io_axi_aw_bits_cache       (awcache          ),
-  .io_axi_aw_bits_prot        (awprot           ),
-  .io_axi_aw_valid            (awvalid          ),
-  .io_axi_aw_ready            (awready          ),
-  .io_axi_w_bits_id           (wid              ),
-  .io_axi_w_bits_data         (wdata            ),
-  .io_axi_w_bits_strb         (wstrb            ),
-  .io_axi_w_bits_last         (wlast            ),
-  .io_axi_w_valid             (wvalid           ),
-  .io_axi_w_ready             (wready           ),
-  .io_axi_b_bits_id           (bid              ),
-  .io_axi_b_bits_resp         (bresp            ),
-  .io_axi_b_valid             (bvalid           ),
-  .io_axi_b_ready             (bready           ),
-  .io_debug_wb_pc             (debug_wb_pc      ),
-  .io_debug_wb_rf_wen         (debug_wb_rf_wen  ),
-  .io_debug_wb_rf_wnum        (debug_wb_rf_wnum ),
-  .io_debug_wb_rf_wdata       (debug_wb_rf_wdata)
-);
-
-endmodule

chisel/playground/resources/mycpu_top_for_soc_simulator.v

@@ -1,132 +0,0 @@
-module mycpu_top (
-    input  [ 5:0]      ext_int,
-    input              aclk,
-    input              aresetn,
-    //axi interface
-
-    //read request
-    output [ 3:0]      arid,
-    output [31:0]      araddr,
-    output [ 7:0]      arlen,
-    output [ 2:0]      arsize,
-    output [ 1:0]      arburst,
-    output [ 1:0]      arlock,
-    output [ 3:0]      arcache,
-    output [ 2:0]      arprot,
-    output             arvalid,
-    input              arready,
-
-    //read response
-    input  [ 3:0]      rid,
-    input  [31:0]      rdata,
-    input  [ 1:0]      rresp,
-    input              rlast,
-    input              rvalid,
-    output             rready,
-
-    //write request
-    output [ 3:0]      awid,
-    output [31:0]      awaddr,
-    output [ 7:0]      awlen,
-    output [ 2:0]      awsize,
-    output [ 1:0]      awburst,
-    output [ 1:0]      awlock,
-    output [ 3:0]      awcache,
-    output [ 2:0]      awprot,
-    output             awvalid,
-    input              awready,
-
-    //write data
-    output [ 3:0]      wid,
-    output [31:0]      wdata,
-    output [ 3:0]      wstrb,
-    output             wlast,
-    output             wvalid,
-    input              wready,
-
-    //write response
-    input  [ 3:0]      bid,
-    input  [ 1:0]      bresp,
-    input              bvalid,
-    output             bready,
-    
-    // trace debug interface
-    output [31:0]      debug_wb_pc,
-    output [ 3:0]      debug_wb_rf_wen,
-    output [ 4:0]      debug_wb_rf_wnum,
-    output [31:0]      debug_wb_rf_wdata,
-    // for soc-simulator
-    output [31:0]      statistic_cpu_soc_cp0_count,
-    output [31:0]      statistic_cpu_soc_cp0_random,
-    output [31:0]      statistic_cpu_soc_cp0_cause,
-    output             statistic_cpu_soc_int,
-    output             statistic_cpu_soc_commit,
-
-    // bpu statistic 
-    output [31:0]      statistic_cpu_bpu_branch,
-    output [31:0]      statistic_cpu_bpu_success,
-
-    // cache statistic
-    output [31:0]      statistic_cache_icache_request,
-    output [31:0]      statistic_cache_icache_hit,
-    output [31:0]      statistic_cache_dcache_request,
-    output [31:0]      statistic_cache_dcache_hit
-);
-
-PuaMips puamips(
-  .clock                                (aclk                           ),
-  .reset                                (~aresetn                       ),
-  .io_ext_int                           (ext_int                        ),
-  .io_axi_ar_bits_id                    (arid                           ),
-  .io_axi_ar_bits_addr                  (araddr                         ),
-  .io_axi_ar_bits_len                   (arlen                          ),
-  .io_axi_ar_bits_size                  (arsize                         ),
-  .io_axi_ar_bits_burst                 (arburst                        ),
-  .io_axi_ar_bits_lock                  (arlock                         ),
-  .io_axi_ar_bits_cache                 (arcache                        ),
-  .io_axi_ar_bits_prot                  (arprot                         ),
-  .io_axi_ar_valid                      (arvalid                        ),
-  .io_axi_ar_ready                      (arready                        ),
-  .io_axi_r_bits_id                     (rid                            ),
-  .io_axi_r_bits_data                   (rdata                          ),
-  .io_axi_r_bits_resp                   (rresp                          ),
-  .io_axi_r_bits_last                   (rlast                          ),
-  .io_axi_r_valid                       (rvalid                         ),
-  .io_axi_r_ready                       (rready                         ),
-  .io_axi_aw_bits_id                    (awid                           ),
-  .io_axi_aw_bits_addr                  (awaddr                         ),
-  .io_axi_aw_bits_len                   (awlen                          ),
-  .io_axi_aw_bits_size                  (awsize                         ),
-  .io_axi_aw_bits_burst                 (awburst                        ),
-  .io_axi_aw_bits_lock                  (awlock                         ),
-  .io_axi_aw_bits_cache                 (awcache                        ),
-  .io_axi_aw_bits_prot                  (awprot                         ),
-  .io_axi_aw_valid                      (awvalid                        ),
-  .io_axi_aw_ready                      (awready                        ),
-  .io_axi_w_bits_id                     (wid                            ),
-  .io_axi_w_bits_data                   (wdata                          ),
-  .io_axi_w_bits_strb                   (wstrb                          ),
-  .io_axi_w_bits_last                   (wlast                          ),
-  .io_axi_w_valid                       (wvalid                         ),
-  .io_axi_w_ready                       (wready                         ),
-  .io_axi_b_bits_id                     (bid                            ),
-  .io_axi_b_bits_resp                   (bresp                          ),
-  .io_axi_b_valid                       (bvalid                         ),
-  .io_axi_b_ready                       (bready                         ),
-  .io_debug_wb_pc                       (debug_wb_pc                    ),
-  .io_debug_wb_rf_wen                   (debug_wb_rf_wen                ),
-  .io_debug_wb_rf_wnum                  (debug_wb_rf_wnum               ),
-  .io_debug_wb_rf_wdata                 (debug_wb_rf_wdata              ),
-  .io_statistic_cpu_soc_cp0_count       (statistic_cpu_soc_cp0_count    ),
-  .io_statistic_cpu_soc_cp0_random      (statistic_cpu_soc_cp0_random   ),
-  .io_statistic_cpu_soc_cp0_cause       (statistic_cpu_soc_cp0_cause    ),
-  .io_statistic_cpu_soc_int             (statistic_cpu_soc_int          ),
-  .io_statistic_cpu_soc_commit          (statistic_cpu_soc_commit       ),
-  .io_statistic_cpu_bpu_success         (statistic_cpu_bpu_success      ),
-  .io_statistic_cpu_bpu_branch          (statistic_cpu_bpu_branch       ),
-  .io_statistic_cache_icache_request    (statistic_cache_icache_request ),
-  .io_statistic_cache_icache_hit        (statistic_cache_icache_hit     ),
-  .io_statistic_cache_dcache_request    (statistic_cache_dcache_request ),
-  .io_statistic_cache_dcache_hit        (statistic_cache_dcache_hit     )
-);
-endmodule

chisel/playground/resources/top_axi_wrapper.v

@@ -46,53 +46,52 @@ module top_axi_wrapper(
     output[63:0]debug_wdata
 );
 
-
+PuaCpu core(
-RiscVTop core(
+    .clock              (clock),
-    .aclk       (clock),
+    .reset              (reset),
-    .aresetn    (~reset),
     // Interrupts
-    .MEI        (MEI), // to PLIC
+    .io_ext_int_ei      (MEI), // to PLIC
-    .MSI        (MSI), // to CLINT
+    .io_ext_int_si      (MSI), // to CLINT
-    .MTI        (MTI), // to CLINT
+    .io_ext_int_ti      (MTI), // to CLINT
     // aw
-    .awid       (MAXI_awid),
+    .io_axi_aw_id       (MAXI_awid),
-    .awaddr     (MAXI_awaddr),
+    .io_axi_aw_addr     (MAXI_awaddr),
-    .awlen      (MAXI_awlen),
+    .io_axi_aw_len      (MAXI_awlen),
-    .awsize     (MAXI_awsize),
+    .io_axi_aw_size     (MAXI_awsize),
-    .awburst    (MAXI_awburst),
+    .io_axi_aw_burst    (MAXI_awburst),
-    .awvalid    (MAXI_awvalid),
+    .io_axi_aw_valid    (MAXI_awvalid),
-    .awready    (MAXI_awready),
+    .io_axi_aw_ready    (MAXI_awready),
     // w
-    .wdata      (MAXI_wdata),
+    .io_axi_w_data      (MAXI_wdata),
-    .wstrb      (MAXI_wstrb),
+    .io_axi_w_strb      (MAXI_wstrb),
-    .wlast      (MAXI_wlast),
+    .io_axi_w_last      (MAXI_wlast),
-    .wvalid     (MAXI_wvalid),
+    .io_axi_w_valid     (MAXI_wvalid),
-    .wready     (MAXI_wready),
+    .io_axi_w_ready     (MAXI_wready),
     // b
-    .bid        (MAXI_bid),
+    .io_axi_b_id        (MAXI_bid),
-    .bresp      (MAXI_bresp),
+    .io_axi_b_resp      (MAXI_bresp),
-    .bvalid     (MAXI_bvalid),
+    .io_axi_b_valid     (MAXI_bvalid),
-    .bready     (MAXI_bready),
+    .io_axi_b_ready     (MAXI_bready),
     // ar
-    .arid       (MAXI_arid),
+    .io_axi_ar_id       (MAXI_arid),
-    .araddr     (MAXI_araddr),
+    .io_axi_ar_addr     (MAXI_araddr),
-    .arlen      (MAXI_arlen),
+    .io_axi_ar_len      (MAXI_arlen),
-    .arsize     (MAXI_arsize),
+    .io_axi_ar_size     (MAXI_arsize),
-    .arburst    (MAXI_arburst),
+    .io_axi_ar_burst    (MAXI_arburst),
-    .arvalid    (MAXI_arvalid),
+    .io_axi_ar_valid    (MAXI_arvalid),
-    .arready    (MAXI_arready),
+    .io_axi_ar_ready    (MAXI_arready),
     // r
-    .rid        (MAXI_rid),
+    .io_axi_r_id        (MAXI_rid),
-    .rdata      (MAXI_rdata),
+    .io_axi_r_data      (MAXI_rdata),
-    .rresp      (MAXI_rresp),
+    .io_axi_r_resp      (MAXI_rresp),
-    .rlast      (MAXI_rlast),
+    .io_axi_r_last      (MAXI_rlast),
-    .rvalid     (MAXI_rvalid),
+    .io_axi_r_valid     (MAXI_rvalid),
-    .rready     (MAXI_rready),
+    .io_axi_r_ready     (MAXI_rready),
     // debug
-    .debug_commit   (debug_commit),
+    .debug_commit       (debug_commit),
-    .debug_pc       (debug_pc),
+    .debug_pc           (debug_pc),
-    .debug_reg_num  (debug_reg_num),
+    .debug_reg_num      (debug_reg_num),
-    .debug_wdata    (debug_wdata)
+    .debug_wdata        (debug_wdata)
 );
 
-endmodule
+endmodule

chisel/playground/src/Core.scala

@@ -59,6 +59,7 @@ class Core(implicit val config: CpuConfig) extends Module {
 
   bpu.decoder.ena                  := ctrl.decoderUnit.allow_to_go
   bpu.decoder.op                   := decoderUnit.bpu.decoded_inst0.op
+  bpu.decoder.fusel                := decoderUnit.bpu.decoded_inst0.fusel
   bpu.decoder.inst                 := decoderUnit.bpu.decoded_inst0.inst
   bpu.decoder.rs1                  := decoderUnit.bpu.decoded_inst0.reg1_raddr
   bpu.decoder.rs2                  := decoderUnit.bpu.decoded_inst0.reg2_raddr
@@ -82,6 +83,8 @@ class Core(implicit val config: CpuConfig) extends Module {
     instFifo.wen(i)             := io.inst.valid(i)
     instFifo.write(i).pc        := io.inst.addr(0) + (i * 4).U
     instFifo.write(i).inst      := io.inst.rdata(i)
+    instFifo.write(i).acc_err   := io.inst.acc_err
+    instFifo.write(i).addr_err  := io.inst.addr_err
   }
 
   decoderUnit.instFifo.info.empty        := instFifo.empty
@@ -135,8 +138,10 @@ class Core(implicit val config: CpuConfig) extends Module {
 
   io.debug <> writeBackUnit.debug
 
-  // io.inst.fence_i        := executeUnit.executeStage.inst0.inst_info.ifence
+  io.inst.fence_i := executeUnit.executeStage.inst0.inst_info.fusel === FuType.mou &&
-  // io.data.fence_i        := memoryUnit.memoryStage.inst0.inst_info.dfence
+    executeUnit.executeStage.inst0.inst_info.op === MOUOpType.fencei
+  io.data.fence_i := memoryUnit.memoryStage.inst0.inst_info.fusel === FuType.mou &&
+    memoryUnit.memoryStage.inst0.inst_info.op === MOUOpType.fencei
   io.inst.en    := !instFifo.full
   io.inst.ready := !ctrl.fetchUnit.allow_to_go
   io.data.ready := !ctrl.memoryUnit.allow_to_go

chisel/playground/src/pipeline/decoder/DecoderUnit.scala

@@ -103,10 +103,6 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
   io.ctrl.inst0.src2.raddr := decoder(0).io.out.inst_info.reg2_raddr
   io.ctrl.branch           := inst0_branch
 
-  val int = WireInit(0.U(INT_WID.W))
-  BoringUtils.addSink(int, "intDecoderUnit")
-  io.executeStage.inst0.ex.interrupt.zip(int.asBools).map { case (x, y) => x := y }
-
   io.executeStage.inst0.valid     := !io.instFifo.info.empty
   io.executeStage.inst0.pc        := pc(0)
   io.executeStage.inst0.inst_info := inst_info(0)
@@ -120,6 +116,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
     forwardCtrl.out.inst(0).src2.rdata,
     decoder(0).io.out.inst_info.imm
   )
+  (0 until (INT_WID)).foreach(i => io.executeStage.inst0.ex.interrupt(i) := io.csr.interrupt(i))
   io.executeStage.inst0.ex.exception.map(_                := false.B)
   io.executeStage.inst0.ex.exception(illegalInstr)        := !inst_info(0).inst_valid
   io.executeStage.inst0.ex.exception(instrAccessFault)    := io.instFifo.inst(0).acc_err
@@ -157,6 +154,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
     forwardCtrl.out.inst(1).src2.rdata,
     decoder(1).io.out.inst_info.imm
   )
+  (0 until (INT_WID)).foreach(i => io.executeStage.inst1.ex.interrupt(i) := io.csr.interrupt(i))
   io.executeStage.inst1.ex.exception.map(_                := false.B)
   io.executeStage.inst1.ex.exception(illegalInstr)        := !inst_info(1).inst_valid
   io.executeStage.inst1.ex.exception(instrAccessFault)    := io.instFifo.inst(1).acc_err

chisel/playground/src/pipeline/execute/ALU.scala

@@ -23,7 +23,6 @@ class Alu extends Module {
   val io = IO(new Bundle {
     val inst_info = Input(new InstInfo())
     val src_info  = Input(new SrcInfo())
-    val csr_rdata = Input(UInt(DATA_WID.W))
     val result    = Output(UInt(DATA_WID.W))
   })
   val op     = io.inst_info.op

chisel/playground/src/pipeline/execute/Csr.scala

@@ -25,22 +25,20 @@ class CsrMemoryUnit(implicit val config: CpuConfig) extends Bundle {
 
 class CsrExecuteUnit(implicit val config: CpuConfig) extends Bundle {
   val in = Input(new Bundle {
-    val valid     = Vec(config.fuNum, Bool())
+    val valid     = Bool()
-    val inst_info = Vec(config.fuNum, new InstInfo())
+    val inst_info = new InstInfo()
-    val src_info  = Vec(config.fuNum, new SrcInfo())
+    val src_info  = new SrcInfo()
-    val wdata     = UInt(DATA_WID.W)
+    val ex        = new ExceptionInfo()
   })
   val out = Output(new Bundle {
-    val rdata    = Vec(config.fuNum, UInt(DATA_WID.W))
+    val rdata = UInt(DATA_WID.W)
-    val trap_ill = Bool()
+    val ex    = new ExceptionInfo()
-    val ex       = Vec(config.fuNum, new ExceptionInfo())
   })
 }
 
 class CsrDecoderUnit extends Bundle {
   val priv_mode = Output(Priv())
-  val irq       = Output(Bool())
+  val interrupt = Output(UInt(INT_WID.W))
-  val irq_type  = Output(UInt(4.W))
 }
 
 class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
@@ -168,32 +166,37 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
     // MaskedRegMap(PmpaddrBase + 3, pmpaddr3, pmpaddrWmask)
   ) //++ perfCntsLoMapping
 
-  // interrupts
+  val priv_mode = RegInit(Priv.m) // 当前特权模式
 
-  val mtip = WireInit(false.B)
+  // interrupts
-  val meip = WireInit(false.B)
+  val mtip = io.ext_int.ti
-  val msip = WireInit(false.B)
+  val meip = io.ext_int.ei
-  BoringUtils.addSink(mtip, "mtip")
+  val msip = io.ext_int.si
-  BoringUtils.addSink(meip, "meip")
-  BoringUtils.addSink(msip, "msip")
   mipWire.t.m := mtip
   mipWire.e.m := meip
   mipWire.s.m := msip
-
+  val seip              = meip
-  val priv_mode = RegInit(Priv.m) // 当前特权模式
+  val mip_has_interrupt = WireInit(mip)
+  mip_has_interrupt.e.s := mip.e.s | seip
+  val interrupt_enable = Wire(UInt(INT_WID.W)) // 不用考虑ideleg
+  interrupt_enable := Fill(
+    INT_WID,
+    (((priv_mode === ModeM) && mstatus.asTypeOf(new Mstatus()).mie) || (priv_mode < ModeM))
+  )
+  io.decoderUnit.interrupt := mie(11, 0) & mip_has_interrupt.asUInt & interrupt_enable.asUInt
 
   // 优先使用inst0的信息
   val exc_sel = io.memoryUnit.in.inst(0).ex.exception.asUInt.orR ||
     !io.memoryUnit.in.inst(1).ex.exception.asUInt.orR
   val pc        = Mux(exc_sel, io.memoryUnit.in.inst(0).pc, io.memoryUnit.in.inst(1).pc)
   val exc       = Mux(exc_sel, io.memoryUnit.in.inst(0).ex, io.memoryUnit.in.inst(1).ex)
-  val valid     = io.executeUnit.in.valid(0)
+  val valid     = io.executeUnit.in.valid
-  val op        = io.executeUnit.in.inst_info(0).op
+  val op        = io.executeUnit.in.inst_info.op
-  val fusel     = io.executeUnit.in.inst_info(0).fusel
+  val fusel     = io.executeUnit.in.inst_info.fusel
-  val addr      = io.executeUnit.in.inst_info(0).inst(31, 20)
+  val addr      = io.executeUnit.in.inst_info.inst(31, 20)
   val rdata     = Wire(UInt(XLEN.W))
-  val src1      = io.executeUnit.in.src_info(0).src1_data
+  val src1      = io.executeUnit.in.src_info.src1_data
-  val csri      = ZeroExtend(io.executeUnit.in.inst_info(0).inst(19, 15), XLEN)
+  val csri      = ZeroExtend(io.executeUnit.in.inst_info.inst(19, 15), XLEN)
   val exe_stall = io.ctrl.exe_stall
   val mem_stall = io.ctrl.mem_stall
   val wdata = LookupTree(
@@ -208,7 +211,6 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
     )
   )
 
-  io.executeUnit.out.trap_ill := false.B
   //val satp_legal  = (wdata.asTypeOf(new Satp()).mode === 0.U) || (wdata.asTypeOf(new Satp()).mode === 8.U)
   val wen            = (valid && op =/= CSROpType.jmp) //&& (addr =/= Satp.U || satp_legal)
   val illegal_mode   = priv_mode < addr(9, 8)
@@ -233,8 +235,13 @@ class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
   val isUret = addr === privUret && op === CSROpType.jmp
   ret := isMret || isSret || isUret
 
-  val csrExceptionVec = Wire(Vec(16, Bool()))
+  io.executeUnit.out.ex                         := io.executeUnit.in.ex
-  csrExceptionVec.map(_         := false.B)
+  io.executeUnit.out.ex.exception(illegalInstr) := (illegal_addr || illegal_access) && wen
-  csrExceptionVec(illegalInstr) := (illegal_addr || illegal_access) && wen
+  io.executeUnit.out.rdata                      := rdata
+
+  io.decoderUnit.priv_mode                      := priv_mode
+
+  io.memoryUnit.out.flush := exc.exception.asUInt.orR || exc.interrupt.asUInt.orR
+  io.memoryUnit.out.flush_pc := mtvec
 
 }

chisel/playground/src/pipeline/execute/ExecuteUnit.scala

@@ -29,7 +29,6 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
           }
         )
       )
-      val inst0_bd = Input(Bool())
     }
     val memoryStage = Output(new ExecuteUnitMemoryUnit())
   })
@@ -44,12 +43,24 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   io.ctrl.branch := io.ctrl.allow_to_go &&
     (io.executeStage.inst0.jb_info.jump_regiser || fu.branch.pred_fail)
 
-  io.csr.in.inst_info(0) := Mux(
+  val csr_sel0 = io.executeStage.inst0.inst_info.fusel === FuType.csr && !io.executeStage.inst0.ex.exception.asUInt.orR
-    !io.executeStage.inst0.ex.exception.asUInt.orR,
+  val csr_sel1 = io.executeStage.inst1.inst_info.fusel === FuType.csr && !io.executeStage.inst1.ex.exception.asUInt.orR
+  io.csr.in.valid := csr_sel0 || csr_sel1
+  io.csr.in.inst_info := Mux(
+    csr_sel0 && !csr_sel1,
     io.executeStage.inst0.inst_info,
-    0.U.asTypeOf(new InstInfo())
+    io.executeStage.inst1.inst_info
+  )
+  io.csr.in.src_info := Mux(
+    csr_sel0 && !csr_sel1,
+    io.executeStage.inst0.src_info,
+    io.executeStage.inst1.src_info
+  )
+  io.csr.in.ex := Mux(
+    csr_sel0 && !csr_sel1,
+    io.executeStage.inst0.ex,
+    io.executeStage.inst1.ex
   )
-  io.csr.in.inst_info(1) := io.executeStage.inst1.inst_info
 
   // input accessMemCtrl
   accessMemCtrl.inst(0).inst_info := io.executeStage.inst0.inst_info
@@ -78,7 +89,6 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   fu.inst(1).inst_info  := io.executeStage.inst1.inst_info
   fu.inst(1).src_info   := io.executeStage.inst1.src_info
   fu.inst(1).ex.in      := io.executeStage.inst1.ex
-  fu.csr_rdata          := io.csr.out.rdata
   fu.branch.pred_branch := io.executeStage.inst0.jb_info.pred_branch
 
   io.bpu.pc               := io.executeStage.inst0.pc
@@ -117,7 +127,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   io.memoryStage.inst0.ex := MuxLookup(io.executeStage.inst0.inst_info.fusel, fu.inst(0).ex.out)(
     Seq(
       FuType.lsu -> accessMemCtrl.inst(0).ex.out,
-      FuType.csr -> io.csr.out.ex(0)
+      FuType.csr -> io.csr.out.ex
     )
   )
 
@@ -131,7 +141,7 @@ class ExecuteUnit(implicit val config: CpuConfig) extends Module {
   io.memoryStage.inst1.ex := MuxLookup(io.executeStage.inst1.inst_info.fusel, fu.inst(1).ex.out)(
     Seq(
       FuType.lsu -> accessMemCtrl.inst(1).ex.out,
-      FuType.csr -> io.csr.out.ex(1)
+      FuType.csr -> io.csr.out.ex
     )
   )
 

chisel/playground/src/pipeline/execute/Fu.scala

@@ -13,7 +13,6 @@ class Fu(implicit val config: CpuConfig) extends Module {
       config.decoderNum,
       new Bundle {
         val pc        = Input(UInt(PC_WID.W))
-        val hilo_wen  = Input(Bool())
         val mul_en    = Input(Bool())
         val div_en    = Input(Bool())
         val inst_info = Input(new InstInfo())
@@ -28,7 +27,6 @@ class Fu(implicit val config: CpuConfig) extends Module {
         })
       }
     )
-    val csr_rdata = Input(Vec(config.fuNum, UInt(DATA_WID.W)))
     val stall_req = Output(Bool())
     val branch = new Bundle {
       val pred_branch = Input(Bool())
@@ -55,7 +53,6 @@ class Fu(implicit val config: CpuConfig) extends Module {
     // alu(i).io.mul.ready         := mul.ready
     // alu(i).io.div.ready         := div.ready
     // alu(i).io.div.result        := div.result
-    alu(i).io.csr_rdata      := io.csr_rdata(i)
     io.inst(i).ex.out        := io.inst(i).ex.in
     io.inst(i).ex.out.exception := io.inst(i).ex.in.exception
   }