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Remove unused code and update variable assignment in Core and Ctrl classes

This commit is contained in:
Liphen 2023-12-11 15:20:40 +08:00
parent cface2454d
commit 6678952dde
4 changed files with 1 additions and 11 deletions
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1
chisel/playground/src/Core.scala
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@ -38,7 +38,6 @@ class Core(implicit val config: CpuConfig) extends Module {
val writeBackStage = Module(new WriteBackStage()).io val writeBackStage = Module(new WriteBackStage()).io
val writeBackUnit = Module(new WriteBackUnit()).io val writeBackUnit = Module(new WriteBackUnit()).io
ctrl.instFifo.has2insts := !(instFifo.empty || instFifo.almost_empty)
ctrl.decoderUnit <> decoderUnit.ctrl ctrl.decoderUnit <> decoderUnit.ctrl
ctrl.executeUnit <> executeUnit.ctrl ctrl.executeUnit <> executeUnit.ctrl
ctrl.memoryUnit <> memoryUnit.ctrl ctrl.memoryUnit <> memoryUnit.ctrl

1
chisel/playground/src/ctrl/Ctrl.scala
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@ -10,7 +10,6 @@ class Ctrl(implicit val config: CpuConfig) extends Module {
val io = IO(new Bundle { val io = IO(new Bundle {
val cacheCtrl = Flipped(new CacheCtrl()) val cacheCtrl = Flipped(new CacheCtrl())
val fetchUnit = Flipped(new FetchUnitCtrl()) val fetchUnit = Flipped(new FetchUnitCtrl())
val instFifo = Flipped(new InstFifoCtrl())
val decoderUnit = Flipped(new DecoderUnitCtrl()) val decoderUnit = Flipped(new DecoderUnitCtrl())
val executeUnit = Flipped(new ExecuteCtrl()) val executeUnit = Flipped(new ExecuteCtrl())
val memoryUnit = Flipped(new MemoryCtrl()) val memoryUnit = Flipped(new MemoryCtrl())

4
chisel/playground/src/defines/Bundles.scala
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@ -61,10 +61,6 @@ class FetchUnitCtrl extends Bundle {
val do_flush = Input(Bool()) val do_flush = Input(Bool())
} }
class InstFifoCtrl extends Bundle {
val has2insts = Output(Bool())
}
class DecoderUnitCtrl extends Bundle { class DecoderUnitCtrl extends Bundle {
val inst0 = Output(new Bundle { val inst0 = Output(new Bundle {
val src1 = new SrcReadSignal() val src1 = new SrcReadSignal()

4
chisel/playground/src/pipeline/execute/Csr.scala
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@ -51,10 +51,6 @@ class CsrDecoderUnit extends Bundle {
class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst { class Csr(implicit val config: CpuConfig) extends Module with HasCSRConst {
val io = IO(new Bundle { val io = IO(new Bundle {
val ext_int = Input(new ExtInterrupt()) val ext_int = Input(new ExtInterrupt())
val ctrl = Input(new Bundle {
val exe_stall = Bool()
val mem_stall = Bool()
})
val decoderUnit = new CsrDecoderUnit() val decoderUnit = new CsrDecoderUnit()
val executeUnit = new CsrExecuteUnit() val executeUnit = new CsrExecuteUnit()
val memoryUnit = new CsrMemoryUnit() val memoryUnit = new CsrMemoryUnit()