refactor: 将ex信息在执行级后省略

chisel/playground/src/Core.scala

@@ -6,7 +6,6 @@ import chisel3.util._
 import defines._
 import defines.Const._
 import pipeline._
-import ctrl._
 
 class Core extends Module {
   val io = IO(new Bundle {

chisel/playground/src/ctrl/Ctrl.scala

@@ -1,4 +1,4 @@
-package cpu.ctrl
+package cpu.pipeline
 
 import chisel3._
 import chisel3.util._

chisel/playground/src/pipeline/decode/DecodeUnit.scala

@@ -13,13 +13,13 @@ class DataForwardToDecodeUnit extends Bundle {
 
 class DecodeUnit extends Module with HasExceptionNO with HasCSRConst {
   val io = IO(new Bundle {
+    val ctrl         = new DecodeUnitCtrl()
     // 输入
     val decodeStage = Flipped(new FetchUnitDecodeUnit())
     val regfile     = new Src12Read()
     val forward     = Input(new DataForwardToDecodeUnit())
     // 输出
     val executeStage = Output(new DecodeUnitExecuteUnit())
-    val ctrl         = new DecodeUnitCtrl()
   })
 
   val decoder = Module(new Decoder()).io

chisel/playground/src/pipeline/execute/ExecuteUnit.scala

@@ -29,7 +29,7 @@ class ExecuteUnit extends Module {
   fu.data.pc       := io.executeStage.data.pc
   fu.data.info     := io.executeStage.data.info
   fu.data.src_info := io.executeStage.data.src_info
-  fu.data.ex.in    := io.executeStage.data.ex
+  fu.data.ex       := io.executeStage.data.ex
 
   io.dataSram <> fu.dataSram
 
@@ -38,11 +38,11 @@ class ExecuteUnit extends Module {
   io.ctrl.flush          := valid && fu.ctrl.flush
   io.ctrl.target         := fu.ctrl.target
 
-  io.memoryStage.data.pc       := io.executeStage.data.pc
+  io.memoryStage.data.pc            := io.executeStage.data.pc
-  io.memoryStage.data.info     := io.executeStage.data.info
+  io.memoryStage.data.info          := io.executeStage.data.info
-  io.memoryStage.data.src_info := io.executeStage.data.src_info
+  io.memoryStage.data.src_info      := io.executeStage.data.src_info
-  io.memoryStage.data.rd_info  := fu.data.rd_info
+  io.memoryStage.data.rd_info       := fu.data.rd_info
-  io.memoryStage.data.ex       := fu.data.ex.out
+  io.memoryStage.data.has_exception := fu.data.has_exception
 
   // 数据前递
   io.decodeUnit.forward.exe.wen   := io.memoryStage.data.info.reg_wen

chisel/playground/src/pipeline/execute/Fu.scala

@@ -9,14 +9,12 @@ import cpu.CpuConfig
 class Fu extends Module {
   val io = IO(new Bundle {
     val data = new Bundle {
-      val pc       = Input(UInt(XLEN.W))
+      val pc            = Input(UInt(XLEN.W))
-      val info     = Input(new Info())
+      val info          = Input(new Info())
-      val src_info = Input(new SrcInfo())
+      val src_info      = Input(new SrcInfo())
-      val rd_info  = Output(new RdInfo())
+      val rd_info       = Output(new RdInfo())
-      val ex = new Bundle {
+      val ex            = Input(new ExceptionInfo())
-        val in  = Input(new ExceptionInfo())
+      val has_exception = Output(Bool())
-        val out = Output(new ExceptionInfo())
-      }
     }
 
     val dataSram = new DataSram()
@@ -49,7 +47,7 @@ class Fu extends Module {
   io.data.rd_info.wdata(FuType.alu) := alu.result
   io.data.rd_info.wdata(FuType.bru) := io.data.pc + 4.U
   io.data.rd_info.wdata(FuType.mdu) := mdu.result
-  io.data.ex.out                    := io.data.ex.in // TODO: add exception handling
+  io.data.has_exception             := HasExcInt(io.data.ex) // TODO: add exception handling
 
   io.ctrl.flush  := bru.out.branch
   io.ctrl.target := bru.out.target

chisel/playground/src/pipeline/memory/MemoryStage.scala

@@ -7,11 +7,11 @@ import cpu.defines.Const._
 import cpu.CpuConfig
 
 class ExeMemData extends Bundle {
-  val pc       = UInt(XLEN.W)
+  val pc            = UInt(XLEN.W)
-  val info     = new Info()
+  val info          = new Info()
-  val rd_info  = new RdInfo()
+  val rd_info       = new RdInfo()
-  val src_info = new SrcInfo()
+  val src_info      = new SrcInfo()
-  val ex       = new ExceptionInfo()
+  val has_exception = Bool()
 }
 
 class ExecuteUnitMemoryUnit extends Bundle {

chisel/playground/src/pipeline/memory/MemoryUnit.scala

@@ -26,5 +26,5 @@ class MemoryUnit extends Module {
   io.writeBackStage.data.info                      := io.memoryStage.data.info
   io.writeBackStage.data.rd_info.wdata             := io.memoryStage.data.rd_info.wdata
   io.writeBackStage.data.rd_info.wdata(FuType.lsu) := rdata
-  io.writeBackStage.data.ex                        := io.memoryStage.data.ex
+  io.writeBackStage.data.has_exception             := io.memoryStage.data.has_exception
 }

chisel/playground/src/pipeline/writeback/WriteBackStage.scala

@@ -7,10 +7,10 @@ import cpu.defines.Const._
 import cpu.CpuConfig
 
 class MemWbData extends Bundle {
-  val pc      = UInt(XLEN.W)
+  val pc            = UInt(XLEN.W)
-  val info    = new Info()
+  val info          = new Info()
-  val rd_info = new RdInfo()
+  val rd_info       = new RdInfo()
-  val ex      = new ExceptionInfo()
+  val has_exception = Bool()
 }
 
 class MemoryUnitWriteBackUnit extends Bundle {
@@ -18,7 +18,7 @@ class MemoryUnitWriteBackUnit extends Bundle {
 }
 class WriteBackStage extends Module {
   val io = IO(new Bundle {
-    val ctrl = Input(new CtrlSignal())
+    val ctrl          = Input(new CtrlSignal())
     val memoryUnit    = Input(new MemoryUnitWriteBackUnit())
     val writeBackUnit = Output(new MemoryUnitWriteBackUnit())
   })

chisel/playground/src/pipeline/writeback/WriteBackUnit.scala

@@ -18,7 +18,7 @@ class WriteBackUnit extends Module {
     io.writeBackStage.data.info.valid &&
       io.ctrl.ctrlSignal.allow_to_go &&
       io.writeBackStage.data.info.reg_wen &&
-      !(HasExcInt(io.writeBackStage.data.ex))
+      !io.writeBackStage.data.has_exception
 
   io.regfile.waddr := io.writeBackStage.data.info.reg_waddr
   io.regfile.wdata := io.writeBackStage.data.rd_info.wdata(io.writeBackStage.data.info.fusel)