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fix(idu): 数据前递时将0寄存器前递的问题

This commit is contained in:
Liphen 2023-11-28 16:04:43 +08:00
parent 8c2bc3e4a7
commit 5f9cbbbb6f
1 changed files with 14 additions and 4 deletions
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18
chisel/playground/src/pipeline/decoder/ForwardCtrl.scala
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@ -31,13 +31,13 @@ class ForwardCtrl(implicit val config: CpuConfig) extends Module {
for (j <- 0 until (config.fuNum)) {
when(
io.in.forward(j).mem.wen &&
io.in.forward(j).mem.waddr === io.in.regfile(i).src1.raddr,
io.in.forward(j).mem.waddr === io.in.regfile(i).src1.raddr
) {
io.out.inst(i).src1.rdata := io.in.forward(j).mem.wdata
}
when(
io.in.forward(j).mem.wen &&
io.in.forward(j).mem.waddr === io.in.regfile(i).src2.raddr,
io.in.forward(j).mem.waddr === io.in.regfile(i).src2.raddr
) {
io.out.inst(i).src2.rdata := io.in.forward(j).mem.wdata
}
@ -49,16 +49,26 @@ class ForwardCtrl(implicit val config: CpuConfig) extends Module {
for (j <- 0 until (config.fuNum)) {
when(
io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg &&
io.in.forward(j).exe.waddr === io.in.regfile(i).src1.raddr,
io.in.forward(j).exe.waddr === io.in.regfile(i).src1.raddr
) {
io.out.inst(i).src1.rdata := io.in.forward(j).exe.wdata
}
when(
io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg &&
io.in.forward(j).exe.waddr === io.in.regfile(i).src2.raddr,
io.in.forward(j).exe.waddr === io.in.regfile(i).src2.raddr
) {
io.out.inst(i).src2.rdata := io.in.forward(j).exe.wdata
}
}
}
// 读零寄存器时，数据为0
(0 until (config.decoderNum)).foreach(i => {
when(io.in.regfile(i).src1.raddr === 0.U) {
io.out.inst(i).src1.rdata := 0.U
}
when(io.in.regfile(i).src2.raddr === 0.U) {
io.out.inst(i).src2.rdata := 0.U
}
})
}