From 5f9cbbbb6f4db0b01bd738f8bd061bc5eb70ea8e Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Tue, 28 Nov 2023 16:04:43 +0800
Subject: [PATCH] =?UTF-8?q?fix(idu):=20=E6=95=B0=E6=8D=AE=E5=89=8D?=
 =?UTF-8?q?=E9=80=92=E6=97=B6=E5=B0=860=E5=AF=84=E5=AD=98=E5=99=A8?=
 =?UTF-8?q?=E5=89=8D=E9=80=92=E7=9A=84=E9=97=AE=E9=A2=98?=
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---
 .../src/pipeline/decoder/ForwardCtrl.scala     | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala b/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala
index 364542b..1916f94 100644
--- a/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala
+++ b/chisel/playground/src/pipeline/decoder/ForwardCtrl.scala
@@ -31,13 +31,13 @@ class ForwardCtrl(implicit val config: CpuConfig) extends Module {
     for (j <- 0 until (config.fuNum)) {
       when(
         io.in.forward(j).mem.wen &&
-          io.in.forward(j).mem.waddr === io.in.regfile(i).src1.raddr,
+          io.in.forward(j).mem.waddr === io.in.regfile(i).src1.raddr
       ) {
         io.out.inst(i).src1.rdata := io.in.forward(j).mem.wdata
       }
       when(
         io.in.forward(j).mem.wen &&
-          io.in.forward(j).mem.waddr === io.in.regfile(i).src2.raddr,
+          io.in.forward(j).mem.waddr === io.in.regfile(i).src2.raddr
       ) {
         io.out.inst(i).src2.rdata := io.in.forward(j).mem.wdata
       }
@@ -49,16 +49,26 @@ class ForwardCtrl(implicit val config: CpuConfig) extends Module {
     for (j <- 0 until (config.fuNum)) {
       when(
         io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg &&
-          io.in.forward(j).exe.waddr === io.in.regfile(i).src1.raddr,
+          io.in.forward(j).exe.waddr === io.in.regfile(i).src1.raddr
       ) {
         io.out.inst(i).src1.rdata := io.in.forward(j).exe.wdata
       }
       when(
         io.in.forward(j).exe.wen && !io.in.forward(j).mem_wreg &&
-          io.in.forward(j).exe.waddr === io.in.regfile(i).src2.raddr,
+          io.in.forward(j).exe.waddr === io.in.regfile(i).src2.raddr
       ) {
         io.out.inst(i).src2.rdata := io.in.forward(j).exe.wdata
       }
     }
   }
+
+  // 读零寄存器时，数据为0
+  (0 until (config.decoderNum)).foreach(i => {
+    when(io.in.regfile(i).src1.raddr === 0.U) {
+      io.out.inst(i).src1.rdata := 0.U
+    }
+    when(io.in.regfile(i).src2.raddr === 0.U) {
+      io.out.inst(i).src2.rdata := 0.U
+    }
+  })
 }