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fix(csr): 在某些条件下重置mprv

This commit is contained in:
Liphen 2024-03-08 17:28:01 +08:00
parent d3a435ac34
commit 5e7a2eb162
1 changed files with 6 additions and 2 deletions
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8
chisel/playground/src/pipeline/execute/fu/Csr.scala
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@ -370,7 +370,9 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
when(isMret) { when(isMret) {
val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus)) val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus)) val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus))
// mstatusNew.mpp.m := ModeU when(mstatusOld.mpp =/= ModeM){
mstatusNew.mprv := false.B
}
mstatusNew.ie.m := mstatusOld.pie.m mstatusNew.ie.m := mstatusOld.pie.m
mode := mstatusOld.mpp mode := mstatusOld.mpp
mstatusNew.pie.m := true.B mstatusNew.pie.m := true.B
@ -383,7 +385,9 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst {
when(isSret) { when(isSret) {
val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus)) val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus))
val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus)) val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus))
// mstatusNew.mpp.m := ModeU when(mstatusOld.spp =/= ModeM){
mstatusNew.mprv := false.B
}
mstatusNew.ie.s := mstatusOld.pie.s mstatusNew.ie.s := mstatusOld.pie.s
mode := Cat(0.U(1.W), mstatusOld.spp) mode := Cat(0.U(1.W), mstatusOld.spp)
mstatusNew.pie.s := true.B mstatusNew.pie.s := true.B