From 5e7a2eb16243ba650ee17fc7096962d375fe8c91 Mon Sep 17 00:00:00 2001 From: Liphen Date: Fri, 8 Mar 2024 17:28:01 +0800 Subject: [PATCH] =?UTF-8?q?fix(csr):=20=E5=9C=A8=E6=9F=90=E4=BA=9B?= =?UTF-8?q?=E6=9D=A1=E4=BB=B6=E4=B8=8B=E9=87=8D=E7=BD=AEmprv?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/execute/fu/Csr.scala | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/chisel/playground/src/pipeline/execute/fu/Csr.scala b/chisel/playground/src/pipeline/execute/fu/Csr.scala index 576ccf3..7d8ceec 100644 --- a/chisel/playground/src/pipeline/execute/fu/Csr.scala +++ b/chisel/playground/src/pipeline/execute/fu/Csr.scala @@ -370,7 +370,9 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst { when(isMret) { val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus)) val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus)) - // mstatusNew.mpp.m := ModeU + when(mstatusOld.mpp =/= ModeM){ + mstatusNew.mprv := false.B + } mstatusNew.ie.m := mstatusOld.pie.m mode := mstatusOld.mpp mstatusNew.pie.m := true.B @@ -383,7 +385,9 @@ class Csr(implicit val cpuConfig: CpuConfig) extends Module with HasCSRConst { when(isSret) { val mstatusOld = WireInit(mstatus.asTypeOf(new Mstatus)) val mstatusNew = WireInit(mstatus.asTypeOf(new Mstatus)) - // mstatusNew.mpp.m := ModeU + when(mstatusOld.spp =/= ModeM){ + mstatusNew.mprv := false.B + } mstatusNew.ie.s := mstatusOld.pie.s mode := Cat(0.U(1.W), mstatusOld.spp) mstatusNew.pie.s := true.B