feat(debug): 增加sram差分测试接口

chisel/playground/resources/top_axi_wrapper.v

@@ -1,97 +0,0 @@
-module top_axi_wrapper(
-    input       clock,
-    input       reset,
-    // Interrupts
-    input       MEI, // to PLIC
-    input       MSI, // to CLINT
-    input       MTI, // to CLINT
-    // aw
-    output [3:0]MAXI_awid,
-    output[31:0]MAXI_awaddr,
-    output [7:0]MAXI_awlen,
-    output [2:0]MAXI_awsize,
-    output [1:0]MAXI_awburst,
-    output      MAXI_awvalid,
-    input       MAXI_awready,
-    // w
-    output[63:0]MAXI_wdata,
-    output [7:0]MAXI_wstrb,
-    output      MAXI_wlast,
-    output      MAXI_wvalid,
-    input       MAXI_wready,
-    // b
-    input  [3:0]MAXI_bid,
-    input  [1:0]MAXI_bresp,
-    input       MAXI_bvalid,
-    output      MAXI_bready,
-    // ar
-    output [3:0]MAXI_arid,
-    output[31:0]MAXI_araddr,
-    output [7:0]MAXI_arlen,
-    output [2:0]MAXI_arsize,
-    output [1:0]MAXI_arburst,
-    output      MAXI_arvalid,
-    input       MAXI_arready,
-    // r
-    input  [3:0]MAXI_rid,
-    input [63:0]MAXI_rdata,
-    input  [1:0]MAXI_rresp,
-    input       MAXI_rlast,
-    input       MAXI_rvalid,
-    output      MAXI_rready,
-    // debug
-    output      debug_commit,
-    output[63:0]debug_pc,
-    output[4:0] debug_reg_num,
-    output[63:0]debug_wdata
-);
-
-PuaCpu core(
-    .clock                    (clock),
-    .reset                    (reset),
-    // Interrupts     
-    .io_ext_int_ei            (MEI), // to PLIC
-    .io_ext_int_si            (MSI), // to CLINT
-    .io_ext_int_ti            (MTI), // to CLINT
-    // aw 
-    .io_axi_aw_bits_id        (MAXI_awid),
-    .io_axi_aw_bits_addr      (MAXI_awaddr),
-    .io_axi_aw_bits_len       (MAXI_awlen),
-    .io_axi_aw_bits_size      (MAXI_awsize),
-    .io_axi_aw_bits_burst     (MAXI_awburst),
-    .io_axi_aw_valid          (MAXI_awvalid),
-    .io_axi_aw_ready          (MAXI_awready),
-    // w 
-    .io_axi_w_bits_data       (MAXI_wdata),
-    .io_axi_w_bits_strb       (MAXI_wstrb),
-    .io_axi_w_bits_last       (MAXI_wlast),
-    .io_axi_w_valid           (MAXI_wvalid),
-    .io_axi_w_ready           (MAXI_wready),
-    // b 
-    .io_axi_b_bits_id         (MAXI_bid),
-    .io_axi_b_bits_resp       (MAXI_bresp),
-    .io_axi_b_valid           (MAXI_bvalid),
-    .io_axi_b_ready           (MAXI_bready),
-    // ar 
-    .io_axi_ar_bits_id        (MAXI_arid),
-    .io_axi_ar_bits_addr      (MAXI_araddr),
-    .io_axi_ar_bits_len       (MAXI_arlen),
-    .io_axi_ar_bits_size      (MAXI_arsize),
-    .io_axi_ar_bits_burst     (MAXI_arburst),
-    .io_axi_ar_valid          (MAXI_arvalid),
-    .io_axi_ar_ready          (MAXI_arready),
-    // r 
-    .io_axi_r_bits_id         (MAXI_rid),
-    .io_axi_r_bits_data       (MAXI_rdata),
-    .io_axi_r_bits_resp       (MAXI_rresp),
-    .io_axi_r_bits_last       (MAXI_rlast),
-    .io_axi_r_valid           (MAXI_rvalid),
-    .io_axi_r_ready           (MAXI_rready),
-    // debug
-    .io_debug_wb_pc           (debug_pc),
-    .io_debug_wb_rf_wen       (debug_commit),
-    .io_debug_wb_rf_wnum      (debug_reg_num),
-    .io_debug_wb_rf_wdata     (debug_wdata)
-);
-
-endmodule

chisel/playground/resources/top_sram_wrapper.v

@@ -20,8 +20,13 @@ module top_sram_wrapper(
     // trace debug interface
     output        debug_commit,
     output [63:0] debug_pc,
-    output [4:0 ] debug_reg_num,
+    output [4:0 ] debug_rf_wnum,
-    output [63:0] debug_wdata
+    output [63:0] debug_rf_wdata,
+    // sram
+    output [7:0]  io_debug_sram_wen,
+    output [31:0] io_debug_sram_waddr,
+    output [63:0] io_debug_sram_wdata
+
 );
 
 PuaCpu core(
@@ -44,10 +49,14 @@ PuaCpu core(
     .io_data_sram_wdata       (data_sram_wdata),
     .io_data_sram_rdata       (data_sram_rdata),
     // debug
-    .io_debug_wb_pc           (debug_pc),
+    .io_debug_pc              (debug_pc),
-    .io_debug_wb_commit       (debug_commit),
+    .io_debug_commit          (debug_commit),
-    .io_debug_wb_rf_wnum      (debug_reg_num),
+    .io_debug_rf_wnum         (debug_rf_wnum),
-    .io_debug_wb_rf_wdata     (debug_wdata)
+    .io_debug_rf_wdata        (debug_rf_wdata),
+    // sram
+    .io_debug_sram_wen        (io_debug_sram_wen),
+    .io_debug_sram_waddr      (io_debug_sram_waddr),
+    .io_debug_sram_wdata      (io_debug_sram_wdata)
 );
 
 endmodule

chisel/playground/src/defines/Bundles.scala

@@ -58,7 +58,7 @@ class CtrlSignal extends Bundle {
 }
 
 class FetchUnitCtrl extends Bundle {
-  val target = Input(UInt(XLEN.W))
+  val target     = Input(UInt(XLEN.W))
   val ctrlSignal = Input(new CtrlSignal())
 }
 
@@ -103,9 +103,15 @@ class DataSram extends Bundle {
   val rdata = Input(UInt(XLEN.W))
 }
 
-class DEBUG extends Bundle {
+class DataSram_DEBUG extends Bundle {
-  val wb_pc       = Output(UInt(XLEN.W))
+  val waddr = UInt(AXI_ADDR_WID.W)
-  val wb_commit   = Output(Bool())
+  val wdata = UInt(XLEN.W)
-  val wb_rf_wnum  = Output(UInt(REG_ADDR_WID.W))
+  val wen   = UInt(AXI_STRB_WID.W)
-  val wb_rf_wdata = Output(UInt(XLEN.W))
+}
+class DEBUG extends Bundle {
+  val pc       = Output(UInt(XLEN.W))
+  val commit   = Output(Bool())
+  val rf_wnum  = Output(UInt(REG_ADDR_WID.W))
+  val rf_wdata = Output(UInt(XLEN.W))
+  val sram     = new DataSram_DEBUG()
 }

chisel/playground/src/pipeline/execute/ExecuteUnit.scala

@@ -32,6 +32,9 @@ class ExecuteUnit extends Module {
   fu.data.ex       := io.executeStage.data.ex
 
   io.dataSram <> fu.dataSram
+  io.memoryStage.sram.wen   := fu.dataSram.wen
+  io.memoryStage.sram.waddr := fu.dataSram.addr
+  io.memoryStage.sram.wdata := fu.dataSram.wdata
 
   io.ctrl.data.is_load   := fusel === FuType.lsu && LSUOpType.isLoad(io.executeStage.data.info.op)
   io.ctrl.data.reg_waddr := io.executeStage.data.info.reg_waddr

chisel/playground/src/pipeline/memory/MemoryStage.scala

@@ -16,6 +16,7 @@ class ExeMemData extends Bundle {
 
 class ExecuteUnitMemoryUnit extends Bundle {
   val data = new ExeMemData()
+  val sram = new DataSram_DEBUG()
 }
 
 class MemoryStage extends Module {
@@ -25,12 +26,16 @@ class MemoryStage extends Module {
     val memoryUnit  = Output(new ExecuteUnitMemoryUnit())
   })
   val data = RegInit(0.U.asTypeOf(new ExeMemData()))
+  val sram = RegInit(0.U.asTypeOf(new DataSram_DEBUG()))
 
   when(io.ctrl.do_flush) {
     data := 0.U.asTypeOf(new ExeMemData())
+    sram := 0.U.asTypeOf(new DataSram_DEBUG())
   }.elsewhen(io.ctrl.allow_to_go) {
     data := io.executeUnit.data
+    sram := io.executeUnit.sram
   }
 
   io.memoryUnit.data := data
+  io.memoryUnit.sram := sram
 }

chisel/playground/src/pipeline/memory/MemoryUnit.scala

@@ -27,4 +27,5 @@ class MemoryUnit extends Module {
   io.writeBackStage.data.rd_info.wdata             := io.memoryStage.data.rd_info.wdata
   io.writeBackStage.data.rd_info.wdata(FuType.lsu) := rdata
   io.writeBackStage.data.has_exception             := io.memoryStage.data.has_exception
+  io.writeBackStage.sram                           := io.memoryStage.sram
 }

chisel/playground/src/pipeline/writeback/WriteBackStage.scala

@@ -15,6 +15,7 @@ class MemWbData extends Bundle {
 
 class MemoryUnitWriteBackUnit extends Bundle {
   val data = new MemWbData()
+  val sram = new DataSram_DEBUG()
 }
 class WriteBackStage extends Module {
   val io = IO(new Bundle {
@@ -24,12 +25,16 @@ class WriteBackStage extends Module {
   })
 
   val data = RegInit(0.U.asTypeOf(new MemWbData()))
+  val sram = RegInit(0.U.asTypeOf(new DataSram_DEBUG()))
 
   when(io.ctrl.do_flush) {
     data := 0.U.asTypeOf(new MemWbData())
+    sram := 0.U.asTypeOf(new DataSram_DEBUG())
   }.elsewhen(io.ctrl.allow_to_go) {
     data := io.memoryUnit.data
+    sram := io.memoryUnit.sram
   }
 
   io.writeBackUnit.data := data
+  io.writeBackUnit.sram := sram
 }

chisel/playground/src/pipeline/writeback/WriteBackUnit.scala

@@ -23,8 +23,9 @@ class WriteBackUnit extends Module {
   io.regfile.waddr := io.writeBackStage.data.info.reg_waddr
   io.regfile.wdata := io.writeBackStage.data.rd_info.wdata(io.writeBackStage.data.info.fusel)
 
-  io.debug.wb_pc       := io.writeBackStage.data.pc
+  io.debug.pc       := io.writeBackStage.data.pc
-  io.debug.wb_commit   := io.writeBackStage.data.info.valid && io.ctrl.ctrlSignal.allow_to_go
+  io.debug.commit   := io.writeBackStage.data.info.valid && io.ctrl.ctrlSignal.allow_to_go
-  io.debug.wb_rf_wnum  := io.regfile.waddr
+  io.debug.rf_wnum  := io.regfile.waddr
-  io.debug.wb_rf_wdata := io.regfile.wdata
+  io.debug.rf_wdata := io.regfile.wdata
+  io.debug.sram     := io.writeBackStage.sram
 }

difftest

@@ -1 +1 @@
-Subproject commit 34a01787d1c5883684aa2d30144f9793e13759a2
+Subproject commit be00525e85796bf0e8361c8d2de46ba57c460231