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fix(exe): 修复mem addr错误

This commit is contained in:
Liphen 2023-11-27 14:55:04 +08:00
parent 4c8b004029
commit 53860c99c6
2 changed files with 24 additions and 20 deletions
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40
chisel/playground/src/cache/DCache.scala vendored
View File

@ -47,26 +47,30 @@ class DCache(implicit config: CpuConfig) extends Module {
io.axi.aw.cache := 0.U io.axi.aw.cache := 0.U
val wvalid = RegInit(false.B) val wvalid = RegInit(false.B)
val wdata = RegInit(0.U(XLEN.W))
val wstrb = RegInit(0.U(4.W))
io.axi.w.id := 1.U io.axi.w.id := 1.U
io.axi.w.data := 0.U io.axi.w.data := wdata
io.axi.w.strb := 0.U io.axi.w.strb := wstrb
io.axi.w.last := 1.U io.axi.w.last := 1.U
io.axi.w.valid := wvalid io.axi.w.valid := wvalid
io.axi.b.ready := 1.U io.axi.b.ready := 1.U
val araddr = RegInit(0.U(32.W)) val araddr = RegInit(0.U(32.W))
val arsize = RegInit(0.U(3.W)) val arsize = RegInit(0.U(3.W))
val arlen = RegInit(0.U(8.W))
val arvalid = RegInit(false.B)
io.axi.ar.id := 1.U io.axi.ar.id := 1.U
io.axi.ar.addr := araddr io.axi.ar.addr := araddr
io.axi.ar.len := 0.U io.axi.ar.len := arlen
io.axi.ar.size := arsize io.axi.ar.size := arsize
io.axi.ar.burst := BURST_INCR.U io.axi.ar.burst := BURST_INCR.U
val arvalid = RegInit(false.B)
io.axi.ar.valid := arvalid io.axi.ar.valid := arvalid
io.axi.ar.prot := 0.U io.axi.ar.prot := 0.U
io.axi.ar.cache := 0.U io.axi.ar.cache := 0.U
io.axi.ar.lock := 0.U io.axi.ar.lock := 0.U
val rready = RegInit(false.B) val rready = RegInit(false.B)
io.axi.r.ready := rready io.axi.r.ready := rready
@ -85,19 +89,19 @@ class DCache(implicit config: CpuConfig) extends Module {
status := s_save status := s_save
}.otherwise { }.otherwise {
when(io.cpu.write) { when(io.cpu.write) {
awaddr := io.cpu.addr(31, 0) awaddr := io.cpu.addr(31, 0)
awsize := Cat(false.B, io.cpu.size) awsize := Cat(false.B, io.cpu.size)
awvalid := true.B awvalid := true.B
io.axi.w.data := io.cpu.wdata wdata := io.cpu.wdata
io.axi.w.strb := wstrb_gen wstrb := wstrb_gen
wvalid := true.B wvalid := true.B
status := s_writeback status := s_writeback
}.otherwise { }.otherwise {
araddr := io.cpu.addr(31, 0) araddr := io.cpu.addr(31, 0)
io.axi.ar.size := Cat(false.B, io.cpu.size) arsize := Cat(false.B, io.cpu.size)
arvalid := true.B arvalid := true.B
rready := true.B rready := true.B
status := s_uncached status := s_uncached
} }
} }
} }

4
chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
View File

@ -44,8 +44,8 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
) )
) )
val mem_addr = Wire(Vec(config.fuNum, UInt(DATA_ADDR_WID.W))) val mem_addr = Wire(Vec(config.fuNum, UInt(DATA_ADDR_WID.W)))
mem_addr(0) := io.inst(0).src_info.src1_data + io.inst(0).src_info.src2_data mem_addr(0) := io.inst(0).src_info.src1_data + io.inst(0).inst_info.imm
mem_addr(1) := io.inst(1).src_info.src1_data + io.inst(1).src_info.src2_data mem_addr(1) := io.inst(1).src_info.src1_data + io.inst(1).inst_info.imm
io.mem.out.addr := Mux1H( io.mem.out.addr := Mux1H(
Seq( Seq(
(io.inst(0).inst_info.fusel === FuType.lsu) -> mem_addr(0), (io.inst(0).inst_info.fusel === FuType.lsu) -> mem_addr(0),