From 53860c99c64e8ccbcb3c8b25c5a56a65b4fc4ba2 Mon Sep 17 00:00:00 2001
From: Liphen <xi.lifeng@qq.com>
Date: Mon, 27 Nov 2023 14:55:04 +0800
Subject: [PATCH] =?UTF-8?q?fix(exe):=20=E4=BF=AE=E5=A4=8Dmem=20addr?=
 =?UTF-8?q?=E9=94=99=E8=AF=AF?=
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---
 chisel/playground/src/cache/DCache.scala      | 40 ++++++++++---------
 .../pipeline/execute/ExeAccessMemCtrl.scala   |  4 +-
 2 files changed, 24 insertions(+), 20 deletions(-)

diff --git a/chisel/playground/src/cache/DCache.scala b/chisel/playground/src/cache/DCache.scala
index f545667..dc806b0 100644
--- a/chisel/playground/src/cache/DCache.scala
+++ b/chisel/playground/src/cache/DCache.scala
@@ -47,26 +47,30 @@ class DCache(implicit config: CpuConfig) extends Module {
   io.axi.aw.cache := 0.U
 
   val wvalid = RegInit(false.B)
+  val wdata  = RegInit(0.U(XLEN.W))
+  val wstrb  = RegInit(0.U(4.W))
   io.axi.w.id    := 1.U
-  io.axi.w.data  := 0.U
-  io.axi.w.strb  := 0.U
+  io.axi.w.data  := wdata
+  io.axi.w.strb  := wstrb
   io.axi.w.last  := 1.U
   io.axi.w.valid := wvalid
 
   io.axi.b.ready := 1.U
 
-  val araddr = RegInit(0.U(32.W))
-  val arsize = RegInit(0.U(3.W))
+  val araddr  = RegInit(0.U(32.W))
+  val arsize  = RegInit(0.U(3.W))
+  val arlen   = RegInit(0.U(8.W))
+  val arvalid = RegInit(false.B)
   io.axi.ar.id    := 1.U
   io.axi.ar.addr  := araddr
-  io.axi.ar.len   := 0.U
+  io.axi.ar.len   := arlen
   io.axi.ar.size  := arsize
   io.axi.ar.burst := BURST_INCR.U
-  val arvalid = RegInit(false.B)
   io.axi.ar.valid := arvalid
   io.axi.ar.prot  := 0.U
   io.axi.ar.cache := 0.U
   io.axi.ar.lock  := 0.U
+
   val rready = RegInit(false.B)
   io.axi.r.ready := rready
 
@@ -85,19 +89,19 @@ class DCache(implicit config: CpuConfig) extends Module {
           status  := s_save
         }.otherwise {
           when(io.cpu.write) {
-            awaddr        := io.cpu.addr(31, 0)
-            awsize        := Cat(false.B, io.cpu.size)
-            awvalid       := true.B
-            io.axi.w.data := io.cpu.wdata
-            io.axi.w.strb := wstrb_gen
-            wvalid        := true.B
-            status        := s_writeback
+            awaddr  := io.cpu.addr(31, 0)
+            awsize  := Cat(false.B, io.cpu.size)
+            awvalid := true.B
+            wdata   := io.cpu.wdata
+            wstrb   := wstrb_gen
+            wvalid  := true.B
+            status  := s_writeback
           }.otherwise {
-            araddr         := io.cpu.addr(31, 0)
-            io.axi.ar.size := Cat(false.B, io.cpu.size)
-            arvalid        := true.B
-            rready         := true.B
-            status         := s_uncached
+            araddr  := io.cpu.addr(31, 0)
+            arsize  := Cat(false.B, io.cpu.size)
+            arvalid := true.B
+            rready  := true.B
+            status  := s_uncached
           }
         }
       }
diff --git a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
index 7cfcad6..a96b36b 100644
--- a/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
+++ b/chisel/playground/src/pipeline/execute/ExeAccessMemCtrl.scala
@@ -44,8 +44,8 @@ class ExeAccessMemCtrl(implicit val config: CpuConfig) extends Module {
     )
   )
   val mem_addr = Wire(Vec(config.fuNum, UInt(DATA_ADDR_WID.W)))
-  mem_addr(0) := io.inst(0).src_info.src1_data + io.inst(0).src_info.src2_data
-  mem_addr(1) := io.inst(1).src_info.src1_data + io.inst(1).src_info.src2_data
+  mem_addr(0) := io.inst(0).src_info.src1_data + io.inst(0).inst_info.imm
+  mem_addr(1) := io.inst(1).src_info.src1_data + io.inst(1).inst_info.imm
   io.mem.out.addr := Mux1H(
     Seq(
       (io.inst(0).inst_info.fusel === FuType.lsu) -> mem_addr(0),