yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix(idu): inst1的ebreak生成有误

This commit is contained in:
Liphen 2023-12-26 14:27:10 +08:00
parent e6a6f250c9
commit 51debc4d27
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
chisel/playground/src/pipeline/decoder/DecoderUnit.scala
View File

@ -168,7 +168,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti
io.executeStage.inst1.ex.exception(instrAddrMisaligned) := pc(1)(1, 0).orR || io.executeStage.inst1.ex.exception(instrAddrMisaligned) := pc(1)(1, 0).orR ||
io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch
io.executeStage.inst1.ex.exception(breakPoint) := info(1).inst(31, 20) === privEbreak && io.executeStage.inst1.ex.exception(breakPoint) := info(1).inst(31, 20) === privEbreak &&
info(1).op === CSROpType.jmp && info(0).fusel === FuType.csr info(1).op === CSROpType.jmp && info(1).fusel === FuType.csr
io.executeStage.inst1.ex.exception(ecallM) := info(1).inst(31, 20) === privEcall && io.executeStage.inst1.ex.exception(ecallM) := info(1).inst(31, 20) === privEcall &&
info(1).op === CSROpType.jmp && mode === ModeM && info(1).fusel === FuType.csr info(1).op === CSROpType.jmp && mode === ModeM && info(1).fusel === FuType.csr
io.executeStage.inst1.ex.exception(ecallS) := info(1).inst(31, 20) === privEcall && io.executeStage.inst1.ex.exception(ecallS) := info(1).inst(31, 20) === privEcall &&