From 51debc4d274a26240d3fd5831c050def484ea88d Mon Sep 17 00:00:00 2001 From: Liphen Date: Tue, 26 Dec 2023 14:27:10 +0800 Subject: [PATCH] =?UTF-8?q?fix(idu):=20inst1=E7=9A=84ebreak=E7=94=9F?= =?UTF-8?q?=E6=88=90=E6=9C=89=E8=AF=AF?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- chisel/playground/src/pipeline/decoder/DecoderUnit.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala index b550d24..4e93809 100644 --- a/chisel/playground/src/pipeline/decoder/DecoderUnit.scala +++ b/chisel/playground/src/pipeline/decoder/DecoderUnit.scala @@ -168,7 +168,7 @@ class DecoderUnit(implicit val config: CpuConfig) extends Module with HasExcepti io.executeStage.inst1.ex.exception(instrAddrMisaligned) := pc(1)(1, 0).orR || io.fetchUnit.target(1, 0).orR && io.fetchUnit.branch io.executeStage.inst1.ex.exception(breakPoint) := info(1).inst(31, 20) === privEbreak && - info(1).op === CSROpType.jmp && info(0).fusel === FuType.csr + info(1).op === CSROpType.jmp && info(1).fusel === FuType.csr io.executeStage.inst1.ex.exception(ecallM) := info(1).inst(31, 20) === privEcall && info(1).op === CSROpType.jmp && mode === ModeM && info(1).fusel === FuType.csr io.executeStage.inst1.ex.exception(ecallS) := info(1).inst(31, 20) === privEcall &&