yystopf
/
riscv-lab
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

修改commit信号

This commit is contained in:
Liphen 2023-11-27 14:18:11 +08:00
parent 152bc91507
commit 4c8b004029
3 changed files with 5 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
chisel/playground/src/pipeline/memory/MemoryUnit.scala
View File

@ -58,6 +58,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
io.writeBackStage.inst0.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata io.writeBackStage.inst0.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex io.writeBackStage.inst0.ex := io.memoryStage.inst0.ex
io.writeBackStage.inst0.ex.exception := io.memoryStage.inst0.ex.exception io.writeBackStage.inst0.ex.exception := io.memoryStage.inst0.ex.exception
io.writeBackStage.inst0.commit := io.memoryStage.inst0.inst_info.valid
io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc io.writeBackStage.inst1.pc := io.memoryStage.inst1.pc
io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info io.writeBackStage.inst1.inst_info := io.memoryStage.inst1.inst_info
@ -65,6 +66,7 @@ class MemoryUnit(implicit val config: CpuConfig) extends Module {
io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata io.writeBackStage.inst1.rd_info.wdata(FuType.lsu) := dataMemoryAccess.memoryUnit.out.rdata
io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex io.writeBackStage.inst1.ex := io.memoryStage.inst1.ex
io.writeBackStage.inst1.ex.exception := io.memoryStage.inst1.ex.exception io.writeBackStage.inst1.ex.exception := io.memoryStage.inst1.ex.exception
io.writeBackStage.inst1.commit := io.memoryStage.inst1.inst_info.valid
io.csr.in.inst(0).pc := io.writeBackStage.inst0.pc io.csr.in.inst(0).pc := io.writeBackStage.inst0.pc
io.csr.in.inst(0).ex := io.writeBackStage.inst0.ex io.csr.in.inst(0).ex := io.writeBackStage.inst0.ex

1
chisel/playground/src/pipeline/writeback/WriteBackStage.scala
View File

@ -10,6 +10,7 @@ class MemWbInst extends Bundle {
val pc = UInt(PC_WID.W) val pc = UInt(PC_WID.W)
val inst_info = new InstInfo() val inst_info = new InstInfo()
val rd_info = new RdInfo() val rd_info = new RdInfo()
val commit = Bool()
val ex = new ExceptionInfo() val ex = new ExceptionInfo()
} }

4
chisel/playground/src/pipeline/writeback/WriteBackUnit.scala
View File

@ -29,11 +29,11 @@ class WriteBackUnit(implicit val config: CpuConfig) extends Module {
if (config.hasCommitBuffer) { if (config.hasCommitBuffer) {
val buffer = Module(new CommitBuffer()).io val buffer = Module(new CommitBuffer()).io
buffer.enq(0).wb_pc := io.writeBackStage.inst0.pc buffer.enq(0).wb_pc := io.writeBackStage.inst0.pc
buffer.enq(0).wb_rf_wen := io.regfile(0).wen buffer.enq(0).wb_rf_wen := io.regfile(0).wen || io.writeBackStage.inst0.commit
buffer.enq(0).wb_rf_wnum := io.regfile(0).waddr buffer.enq(0).wb_rf_wnum := io.regfile(0).waddr
buffer.enq(0).wb_rf_wdata := io.regfile(0).wdata buffer.enq(0).wb_rf_wdata := io.regfile(0).wdata
buffer.enq(1).wb_pc := io.writeBackStage.inst1.pc buffer.enq(1).wb_pc := io.writeBackStage.inst1.pc
buffer.enq(1).wb_rf_wen := io.regfile(1).wen buffer.enq(1).wb_rf_wen := io.regfile(1).wen || io.writeBackStage.inst1.commit
buffer.enq(1).wb_rf_wnum := io.regfile(1).waddr buffer.enq(1).wb_rf_wnum := io.regfile(1).waddr
buffer.enq(1).wb_rf_wdata := io.regfile(1).wdata buffer.enq(1).wb_rf_wdata := io.regfile(1).wdata
buffer.flush := io.ctrl.do_flush buffer.flush := io.ctrl.do_flush